View GW80314GSSL7NK_7379994.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel ? gw80314 i/o companion chip datasheet product features companion chip for the intel ? 80200 processor based on intel xscale ? microarchitecture (arm* architecture compliant?no integrated core) internal non-blocking, high-speed switch fabric two embedded pci-x ports intel ? 80200 processor interface supporting up to two processors with low-latency path to the sdram. two 10/100/1000 mbit ethernet controllers providing descriptor-based access to or from any internal port including sdram sdr/ddr sdram controller with data queueing to allow the increased performance of ddr memory openpic-based multi-function interrupt controller (mpic) peripheral bus interface providing a generic parallel port, access to flash, and access to other types of external memory two 16550-compatible uarts with 16-byte transmit and receive fifos i 2 c two-wire interface for initial configuration or saving vital product data 1 mb of internal high-speed static ram for higher-speed access. order number: 273757-003us november 2004
intel? gw80314 i/o companion chip 2 datasheet information in this document is provided in connection with intel? products. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty relating to sale and/or use of intel products, including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. intel products are not intended for use in medical, life saving , life sustaining, critical control or safety systems, or in nuc lear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? gw80314 companion chip may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. this datasheet as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license. the information in this manual is furnished for informational use only, is subject to change without notice, and shoul d not be construed as a commitment by intel corporation. intel corporation assumes no responsibility or liability for any errors or inaccuracies that m ay appear in this document or any software that may be provided in association with this document. except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted i n any form or by any means without the express written consent of intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct media, dialogic, dm3, etherexpress, etox, flashfile , i386, i486, i960, icomp, instantip, intel, intel centrino, intel logo, intel3 86, intel486, intel740, inteldx2, inteldx4, intelsx2, intel cr eate & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, inte l netstructure, intel play, intel play l ogo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, in tel xscale, iplink, itanium, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2004, intel corporation
intel? gw80314 i/o companion chip datasheet 3 contents 1.0 introduction................................................................................................................ ......... 9 1.1 terminology.........................................................................................................10 1.2 other relevant documents .................................................................................11 2.0 features .................................................................................................................... .......12 2.1 switch fabric unit ...............................................................................................12 2.2 pci-x interface....................................................................................................12 2.3 ciu interface .......................................................................................................13 2.4 sdram controller...............................................................................................14 2.5 dma/xor engine ...............................................................................................15 2.6 gigabit ethernet (gige) interface ........................................................................16 2.7 interrupt controller ..............................................................................................17 2.8 general purpose i/o (gpio) block .....................................................................18 3.0 package information ........................................................................................................1 9 3.1 package introduction...........................................................................................19 3.2 package thermal specifications .........................................................................64 3.3 socket information ..............................................................................................66 4.0 electrical specifications................................................................................................... .68 4.1 absolute maximum ratings.................................................................................68 4.2 pll supply pin requirements ............................................................................69 4.3 targeted dc specifications.................................................................................70 4.4 targeted ac specifications.................................................................................71 4.5 ac timing waveforms ........................................................................................82 4.6 ac test conditions .............................................................................................85 4.7 power sequencing ..............................................................................................87
intel? gw80314 i/o companion chip 4 datasheet figures 1 intel ? gw80314 i/o processor block diagram ..................................................... 9 2 1025-lead hsbga package drawing ................................................................ 41 3 ball map - left side - top view........................................................................... 42 4 ball map - right side - top view ........................................................................ 43 5 intel ? gw80314 i/o processor pll supply decoupling network....................... 69 6 address window signal timing diagram ............................................................ 78 7 data window signal timing diagram ................................................................. 79 8 address to read data timing diagram .............................................................. 79 9 input timing measurement waveforms .............................................................. 82 10 output timing measurement waveforms ........................................................... 82 11 i 2 c interface signal timings................................................................................ 83 12 ddr sdram write timings ............................................................................... 83 13 ddr sdram read timings ............................................................................... 84 14 ac test load for all signals except pci and ddr sdram............................... 85 15 pci/pci-x tov(max) rising edge ac test load............................................... 85 16 pci/pci-x tov(max) falling edge ac test load .............................................. 86 17 pci/pci-x tov(min) ac test load .................................................................... 86 18 correct power sequence for v dd33 , v dd25 , and v dd12 ................................................ 87
intel? gw80314 i/o companion chip datasheet 5 tables 1 terms and acronyms ..........................................................................................10 2 related documentation.......................................................................................11 3 signal type definitions........................................................................................19 4intel xscale ? microprocessor bus signals..........................................................20 5 sdram signals...................................................................................................21 6 gige signals........................................................................................................22 7 peripheral bus interface signals .........................................................................24 8 p1 pci/x signals.................................................................................................25 9 p2 pci/x signals.................................................................................................27 10 p1 hot swap signals...........................................................................................29 11 p2 hot swap signals...........................................................................................29 12 interrupt controller signals..................................................................................29 13 uart signals......................................................................................................30 14 i 2 c signals ..........................................................................................................31 15 miscellaneous signals........................................................................................31 16 test signals.........................................................................................................32 17 pll power signals ..............................................................................................32 18 power supplies ...................................................................................................33 19 signal pin mode behavior ...................................................................................34 20 1025-lead hsbga package ? alphabetical ball listing ..................................44 21 1025-lead hsbga package ? alphabetical signal listing ...............................54 22 thermal simulation data for the intel ? gw80314 i/o processor........................65 23 socket-header vendor........................................................................................66 24 burn-in socket vendor ........................................................................................67 25 shipping tray vendor..........................................................................................67 26 maximum temperature and voltage ratings......................................................68 27 operating conditions...........................................................................................68 28 dc characteristics ..............................................................................................70 29 pci/x clock timings ...........................................................................................71 30 ddr sdram clock timings ...............................................................................71 31 intel xscale ? microprocessor clock timings ......................................................72 32 ac specifications for mii management interface ................................................72 33 ac specifications for g/mii and tbi interface.....................................................73 34 ac specifications for pci/x interface..................................................................74 35 ac specifications for ddr sdram interface .....................................................75 36 ac specifications for intel xscale ? microprocessor interface ............................75 37 ac specifications for uart interface .................................................................76 38 pbi interface timing............................................................................................77 39 ac specifications for i 2 c interface ......................................................................80 40 boundary scan test signal timings ...................................................................81 41 ac measurement conditions ..............................................................................85
intel? gw80314 i/o companion chip 6 datasheet revision history date revision description november 2004 003 changed maximum operation temperature from 105 o to 85 o in section 3.2 removed thermal parameters 1 and 3 from section 3.2.1 removed a portion of environmental conditions information and thermal data information from table 22. removed section 3.2.2, ambient temperature. removed section 3.2.4, thermal resistance. updated case temperature maximum rating in table 26. removed ambient temperature information from table 27. june 2004 002 updated for b1 stepping. september 2003 001 initial document.
intel? gw80314 i/o companion chip datasheet 7
intel? gw80314 i/o companion chip 8 datasheet this page intentionally left blank
intel? gw80314 i/o companion chip introduction datasheet 9 1.0 introduction this is the intel ? gw80314 i/o processor datasheet . this document contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. detailed functional descriptions other than parametric performance are published in the intel ? gw80314 i/o processor developer manual . figure 1 shows a block diagram. this bridge is designed as a fabric centric, any- port-to-any-port bridge. a ll transactions are placed into fabric packets and routed via address-based port selection to another fabric port. the bridge is based on the ?store and forward? concept, where transactions are buffered at the incoming port. when a packet is complete, the incoming port kno ws the size of the packet, and it can be burst across the fabric to the outgoing port. as the timing of the packet is deterministic at the outgoing port, the transaction can be started at the outgoing port as soon as the header arrives. all outgoing figure 1. intel ? gw80314 i/o processor block diagram b1342-01 32-bit address / 64-bit data 100 mhz operation jtag sram registers host port 4 chip selects 64-72 bit / 200 mhz ddr memory dma crc32c xor intel ? 80200 bus interface switching fabric ddr interface pci-x 10/100/1g ethernet pci-x uarts interrupt controller 4 timers i 2 c
intel? gw80314 i/o companion chip introduction 10 datasheet ports can buffer incoming packets to allow for de layed access to the external bus. to limit the latency and to provide a certain quality of service, the internal packets are limited to 256 bytes in size. larger pci transactions are broken into 256-byte transactions at the pci port. 1.1 terminology the following terms are used in this document. table 1. terms and acronyms term/acronym description bar pci-x base address register dma direct memory address embedded configuration causing the pci-x block to provide bars and address translation mechanism to pci-x g/mii gigabit media independent interface lvttl low-voltage transistor-transistor logic mac media access controller mib management information base pci transfers, interfaces or logic that are pci local bus specification, revision 2.3 compatible pci/x used to signify either/or pci or pci-x designation. pci-x transfers, interfaces or logic that may be either pci local bus specification, revision 2.3 or pci-x addendum to the pci local bus specification, revision 1.0a compatible phy physical connection device pma physical media attachment pmd physical media device primary a device with the pci port attached to the pr ocessor bus side in a homogeneous, transparent system. rmon remote monitoring rx receiver secondary a device with the pci port not attached to t he host processor in a homogeneous, transparent system. snmp simple network management protocol sttl schottky transistor-transistor logic tbi ten-bit interface transparent configuration causing the pci/x block to use base and limit registers for pci-x side addressing. tx transmitter vlan virtual local area network
intel? gw80314 i/o companion chip introduction datasheet 11 1.2 other relevant documents table 2. related documentation document title document# / contact intel ? 80312 i/o companion chip developer?s manual 273410 intel ? 80312 i/o companion chip specification update 273416 intel ? 80200 processor based on intel xscale ? microarchitecture developer?s manual 273411 intel ? 80310 i/o processor chipset with intel xscale ? microarchitecture design guide 273354 intel ? 80200 processor based on intel xscale ? microarchitecture datasheet 273414 intel ? 80200 processor based on intel xscale ? microarchitecture specification update 273415 pci local bus specification, revision 2.2 pci special interest group 1-800-433-5177 http://www.pcisig.com/home pci-x addendum to the pci local bus specification, revision 1.0a pci-to-pci bridge architecture specification, revision 1.1 pci system design guide , revision 1.0 pci hot-plug specification, revision 1.0 pci bus power management interface specification , revision 1.1 openpic specification revision 1.2 i 2 c peripherals for microcontrollers philips semiconductors http://www.semiconductors.philips.com/ buses/i2c/ advanced configuration and powe r interface specification, revision 1.0 (acpi) http://www.acpi.info/spec10b.htm note: also see the intel ? product website at http://developer.intel.com/design/iio/ .
intel? gw80314 i/o companion chip features 12 datasheet 2.0 features the intel ? gw80314 i/o processor (gw80314) is an i/o companion ch ip for the intel ? 80200 processor (80200) with an intelligent pci-x bridge and gigabit ethernet access. 2.1 switch fabric unit the purpose of the switch fabric network (sfn) is to provide an interconnect fabric that is useful for on-chip communications between the blocks within the gw80314. the switch fabric unit includes the following features: ? high-performance interconnect fabric for communication between gw80314 blocks ? consistent port definition that is independent of the fabric implementation ? protocol independent of fabric pipeline depth ? three transaction flows using four priority levels ? 64-bit local address ? four or six deep 256-byte transaction queues (1 k for pci-x and sdram) (mode dependent) ? port addressing supports up to 16 sfn ports 2.2 pci-x interface the pci/x block provides an interface to the sfn (internal switch fabric). it is able to convey transactions from the internal sfn fabric to a pc i/x bus and transactions from a pci/x bus to the internal switch fabric. the pci/x block also has the capability to tunnel through the sfn fabric to the other pci/x block on the fabric providing a pseudo-transparent pci-to-pci bridge. this capability is available in the gw80314 as two separate pci/x blocks are integrated. the pci-x block provides the following functions: ? 64-bit capable pci/x interface ? secondary pci arbiter ? compactpci hot swap controller ? control and status registers
intel? gw80314 i/o companion chip features datasheet 13 2.3 ciu interface the intel ? 80200 processor (80200) bus core interface unit (ciu) provides a bridge between the 80200 bus and the switch fabric, an sdram controller, and 1 mb of on chip sram. it has a queuing mechanism to store requests from up to two 80200s. the requests from a given 80200 are completed on the 80200 bus in the order in which they are received. the ciu has the following features: ? up to two 80200 on the processor bus ? up to four read or write requests from each processor ? strict ordering rules for each processor ? optional ecc for processor bus data ? up to four base address registers for the switch fabric ? configurable software reset for the ciu and 80200 processors on startup ? configurable with and without 1 mbyte embedded sram ? reset output for 80200 processors ? one base address register for the 1 mb on-chip sram ? switch fabric access to sram ? 64-bit aligned data words ? 32-bit address decode ? 80200 external bus ecc protection ? two-cycle wait states for write transactions to the sram from the processor bus ? three-cycle wait states for read transactio ns to the sram from the processor bus the ciu does not have the following features: ? locked transactions ? strict ordering rules between processors
intel? gw80314 i/o companion chip features 14 datasheet 2.4 sdram controller the sdram controller core provides an interface to single and double data rate sdram. the sdram controller core has the following features ? synchronous sdram interface for pc100, pc200, and pc1600 ? two-port (64-bit data, 36-bit address) concurrent access to memory ? internal arbiter with programmable priority for each port ? one-port (32-bit data, 18-bit address) access to registers ? supports up to four physical (eight logical) banks ? supports up to 32 bank interleaving (i.e., 32 pages open simultaneously) ? flexible row and column address ? optional ecc (single-bit error correction, multi-bit error detection) ? i/o interface compatib le with ddr sdram ? i 2 c master only interface for dimm detection ? digital dll for automatic dqs timing recovery
intel? gw80314 i/o companion chip features datasheet 15 2.5 dma/xor engine the dma/xor engine has four identical channe ls operating independently. each channel can function as a dma engine or as an xor engine. as a dma engine, it can transfer data from any port to any port and provide crc calculation on the transferred data. as an xor engine, it can perform xor operations on multiple blocks of data, memory fill operation, and parity checking operation. for the dma data transfer and xor oper ation, a channel can be configured to operate in direct mode (single operation) or linked-list mode (multiple operations by stepping through a linked series of command packets in external memory). this dma/xor engine supports unaligned data transfers. the alignment or unalignment of data is the responsibility of the dma/xor engine. the dma/xor registers specify the source, destination, command packet address, mode of operation, the type of mapping to achieve the proper byte alignment, and the byte count for a transaction. note that the maximum byte count is 16 mbytes. all dma operations are assumed to be to prefetchable memory. the dma/xor engine has the following features: ? four-channel support. each channel operates independently. ? data transfer to and from any port as a dma engine ? xor operation, memory fill, and parity checking as an xor engine ? scatter gather (or linked-list) and direct modes ? xor operation of up to 16 blocks of data ? directly fill the store queue with the first block of xor data (optional) ? interrupt on completed segment, chain, and error ? mode-selectable byte alignment on transferred data ? calculate crc on the dma transferred data based on the crc-32c algorithm required by the iscsi specification ? pipeline read requests or read and write requests for better performance ? go/stop/halt control of data transfer operation
intel? gw80314 i/o companion chip features 16 datasheet 2.6 gigabit ethernet (gige) interface the ethernet block is made up of four major sub-blocks. it includes two gigabit ethernet interfaces, e0 and e1. there is a single manage ment interface to manage the two phy devices. each ethernet interface has its own statistics monito r that tracks and reports key interface statistics. each ethernet interface supports a 256-entry hash table for address filtering. each ethernet interface is bridged to the sfn interface domain through a 2k byte transmit fifo and a 4k byte receive fifo. there are four independent dma en gines to support transmit and receive data flows for both ethernet interfaces. the dma engine s rely on descriptors set up in memory, the memory map of the device, and are accessed thro ugh the sfn interface. the dma arbiter handles arbitration for the sfn interface. a register bus interface is provided for the register access and status monitor control. the gige interface has the following features: ? full support for 10/100/1000 mbits/s ethernet standards ieee 802.3, 802.3u, 802.3x, 802.3z, 802.3ac ? full/half-duplex support at 10/100 mbits/s, full-duplex only gigabit ethernet support ? mac control sublayer w/pause, extended opcode support ? mii management with suppressed preamble, sequential cycle, variable clock features ? 8-bit mac engine optimized for size, reduced latency ? optional half-duplex back-pressure (10/100 mbits/s only) ? hash table support for packet filtering ? vlan packet filtering support ? standard register read/write interface ? 2k/4k transmit/receive fifos for data flow synchronization ? two independent dma channels per ethernet port: one transmit and one receive ? four transmit priority descriptor queues controlled via transmit priority tagging ? four receive priority descriptor queues controlled by receive packet filtering priority ? collisions detect and retransmit error handling ? phy management interface ? statistics monitoring and logging: support for rmon mib group 1, rmon mib group 2 if table counters, rmon mib group3, rmon mib group 9, rmon mib 2, and the dot 3 ethernet mib
intel? gw80314 i/o companion chip features datasheet 17 2.7 interrupt controller the interrupt controller is a programmable, register based, and multiple port design that meets openpic specification, revision 1.2. the interrupt controller has the following features: ? support for two intel ? 80200 processors ? sixteen interrupt priority levels (0 to 15) ? level/edge sensibility programmable for 24 irq inputs ? level/edge sensibility programmable for four output pins ? up to 24 input interrupt pins ? up to four output interrupt pins ? four doorbell registers for additional interrupts ? four general-purpose mailbox registers ? four global precision timers ? all registers are read/write 32 bits based ? multiple delivery modes are supported: ? directed-single destination ? directed-multicast ? distributed-multiple destination ? nesting of interrupt events ? spurious vector generation capable ? soft set override for all input sources (maximum 24) ? processor initialization registers ? all registers are at ?known reset state? on power-up
intel? gw80314 i/o companion chip features 18 datasheet 2.8 general purpose i/o (gpio) block the gpio block contains the general purpose i/ o functions available in the gw80314. they include: ? two 16450-compatible uarts with 16-byte incoming and 16-byte outgoing fifos ? one general-purpose i 2 c interface port used for initialization and storing of pci vpd data ? one 8-bit general-purpose parallel i/o port (shared with uart pins) ? one configurable 8-, 16-, or 32-bit periph eral bus interface for interfacing to external sram/rom all the interfaces are configurable via the internal configuration bus.
intel? gw80314 i/o companion chip package information datasheet 19 3.0 package information 3.1 package introduction the gw80314 is offered in a 1025-lead hsbga (heat slug ball grid array) thermally enhanced package. this is a perimeter array package with 904 ball connections in the outer area of the package and a square 11x11 grid of ball connec tions in the middle area of the package. see figure 2 ?1025-lead hsbga package drawing? on page 41 . 3.1.1 functional si gnal definitions signals are classified accordi ng to the types defined in table 3 . table 3. signal type definitions signal type definition i standard input only signal. io standard tristate input/output i(pd) standard input only signal with internal pull down. i(pu) standard input only signal with internal pull up. ai analog input signal o standard output only signal. od open drain output that allows mult iple devices to share as a wire-or to standard tristate output only signal. tio standard tristate input/output signal. io(od) open drain input/output that allows multiple devices to share as a wir e-or when it is used as output. s supply pin, either a v cc or v ss .
intel? gw80314 i/o companion chip package information 20 datasheet 3.1.2 intel xscale ? microprocessor bus signals this section describes the gw80314 intel xscale ? microprocessor signals which are 3.3 v lvttl compatible. notes: 1. for single processor configuration, xs_hlda[0] should be tied low and xs_hlda[1] should be tied high. table 4. intel xscale ? microprocessor bus signals pin name count pin type description xs_a[15:0] 16 i address: during the first cycle of the issue phase, it carries the upper 16 bits of the address for the access. during the second cycle of the issues phase, it carries the lower 16 bits of the address. xs_abort 1 o transaction abort: indicates t he next transaction on the data bus is aborted. xs_be[7:0] 8 io processor bus byte enables. xs_clk 1 io intel xscale ? microprocessor bus clock: output clock for intel xscale ? microprocessor interface and sdram controll er. this pin acts as an input in scan mode. xs_cwf/ dbuswidth 1 o critical word first: indicates the order in which the current 32-byte read burst is returning. also when the intel xscale ? microprocessor bus is in reset this signal is driven low to indicated data bus width is 64-bit. xs_dq[63:0] 64 io data bus. xs_dvalid[1:0] 2 o data valid: one for each intel xscale ? microprocessor on the bus. when asserted high, it indicates that two cycles later, data is valid on xs_dq, xs_be, and xs_ecc. xs_hold[1:0] 2 o signal to intel xscale ? microprocessor to request intel xscale ? microprocessor to release the intel xscale ? microprocessor bus. xs_hlda[1:0] 1 2 i signal from intel xscale ? microprocessor to acknowledge the release of the intel xscale ? microprocessor bus in response to the assertion of the corresponding xs_hold signal. xs_ecc[7:0] 8 io data check bits for intel xscale ? microprocessor ecc bus protect. xs_fiq[1]/pwrup_sd_ byp (configuration pin) 1 io interrupt: indicates a fast interrupt to processor 1. during power-up, this pin is latched at the rising edge of reset and used to enable the sdram pll bypass mode when latched high. xs_fiq[0] 1 o interrupt: indicates a fast interrupt to processor 0. xs_irq[1]/ pwrup_xs_byp (configuration pin) 1 io interrupt: indicates a interrupt to processor 1. during power-up, this pin is latched at the rising edge of reset and is used to enable the intel xscale ? microprocessor pll bypass mode when latched high. xs_irq[0]/ pwrup_fadj configuration pin 1 io interrupt: indicates a interrupt to processor 0. during power-up, this pin is used to program intel xscale ? microprocessor pll frequency adjust logic. ? pwrup_fadj = 0, intel xscale ? pll frequency = 3/4 * sfn_clk. ? pwrup_fadj = 1, intel xscale ? pll frequency = sfn_clk. xs_len[2:0] 3 i control and length access: during the first cycle of the issue phase: ? xs_len[2] (ads#) the start of a bus request. ? xs_len[0] (w/r#) indicates whet her the current request is a read (xs_len[0] = 0) or a write (xs_len[0] =1). during the second cycle of the issue phase: ? xs_len[2:0] indicates the length of the request. xs_reset# 1 o reset pin: when output is low the intel xscale ? microprocessor bus is reset and intel xscale ? microprocessor interface is in reset. intel xscale ? microprocessor pin count 113
intel? gw80314 i/o companion chip package information datasheet 21 3.1.3 sdram controller signals this section describes signals for the gw80314 sdram controller. signals in this group are sstl compatible. table 5. sdram signals pin name count pin type description sd_a[13:0] 14 to address: address and command bus sd_ba[1:0] 2 to bank address : indicates to which bank an active, read, write, or precharge command is being applied. sd_cas# 1 to column address strobe : sd_cas#, sd_ras#, and sd_we# identify the command being sent to the dram devices. sd_clk[3:0] 4 to clock out: clock outputs for sdram dimms. all address and control signals are valid on the positive edge of sd_clk. sd_clk#[3:0] 4 to clock out inverted: clock outputs for sdram dimms sd_clken 1 to clock enable sd_ckfbi 1 i ddr sdram system flight time removal feedback input. sd_ckfbo 1 to ddr sdram system flight time removal feedback output. sd_cs#[7:0] 8 to chip select: enable indicating the command on sd_cas#, sd_ras#, and sd_we# is valid. sd_dq[63:0] 64 io data bus: output with write to ram, and input with read from ram. sd_dqs/dm[17:9] 9 io high data strobe/data mask: output with write to ram, and input with read from ram. edge-aligned with read data, and center-aligned with write data. used as data mask bits in 8-bit/16- bit wide ram ddr systems that require only 9 strobes. sd_dqs[8] 1 io low ecc data strobe: output with write to ram, and input with read from ram. edge-aligned with read data, and center-aligned with write data. sd_dqs[7:0] 8 io low data strobe: output with write to ram, and input with read from ram. edge-aligned with read data, and center-aligned with write data. sd_ecc/dm[7:0] 8 io ecc: indicates which bytes on a write are to be updated or the error detection and correction bits. sd_i2c_clk 1 od serial clock: eeprom serial clock for serial dimm recognition. internally pulled high. sd_i2c_sda 1 io(od) serial data: eeprom serial data line serial dimm recognition. internally pulled high. sd_ras# 1 to row address strobe : sd_cas#, sd_ras,# and sd_we# identify the command being sent to the dram devices. sd_vref 1 ai input threshold reference for the interface used on the ddr interface. sd_we# 1 to write enable: sd_cas#, sd_ras#, and sd_we# identify the command being sent to the dram devices. sd_pwrdelay 1 i indicates healthy power supply. when high during chip reset, the memory controller executes a power failure sequence. ddr pin count 132
intel? gw80314 i/o companion chip package information 22 datasheet 3.1.4 dual-gigabit ethernet (gige) interface signals this section describes signals for the gw80314 dual-ethernet controller. signals in this group are 3.3 v lvttl compatible. table 6. gige signals (sheet 1 of 3) pin name count pin type description port 0 e0_tcg[3:0] 4 to all modes: transmit code group lower nibble. e0_tcg[7:4] 4 to gmii mode: transmit code group upper nibble. tbi mode: transmit code group upper nibble. e0_tcg[8] 1 to mii mode: transmit enable. this signal is synchronous to e0_tx_clk and provides precise framing for data carried on e0_tcg[3:0] for the external pma. it is asserted when e0_tcg[3:0] contains valid data to be transmitted. g/mii mode: transmit enable. this signal is synchronous to gtx_clk and provides precise framing for data carried on e0_tcg[7:0] for the external pma. it is asserted when e0_tcg[7:0] contains valid data to be transmitted. tbi mode: transmit code group bit 8. synchronous to gtx_clk. e0_tcg[9] 1 to mii mode: transmit error. this signal is synchronous to e0_tx_clk and provides error indications. g/mii mode: transmit error. this signal is synchronous to gtx_clk and provides error indications. tbi mode: transmit code group bit 9. synchronous to gtx_clk. e0_rcg[3:0] 4 i all modes: receive code group lower nibble. this is a group of four signals, sourced from an external pma, that contains data aligned on nibble boundaries and are driven synchronous to the e0_clk. e0_rcg[3] is the most significant bit and e0_rcg[0] is the least significant bit. e0_rcg[7:4] 4 i g/mii mode: receive code group upper nibble this is a group of four signals, sourced from an external pma, that contains data aligned on byte boundaries and are driven synchronous to the e0_clk. e0_rcg[7] is most significant bit. tbi mode: receive code group upper nibble. e0_rcg[8] 1 i g/mii modes: receive data valid. this indicates that the external pma is presenting recovered and decoded nibbles on the e0_rcg signals, and that e0_clk is synchronous to the recovered data in 100 mb/s and 1000 mb/s operation. this signal encompasses the frame, starting with the start-of-frame delimiter (jk) and excluding any end-of-frame delimiter (tr). tbi mode: transmit code group bit 8. e0_rcg[9] 1 i g/mii modes: receive error. this signal is synchronous to e0_clk/e0_pma_clk0 and provides media error indications. tbi mode: transmit code group bit 9. e0_pcrs_sdet 1 i g/mii modes: ph y carrier sense indication. tbi mode: indicates signals detected. e0_pcol_rbcm 1 io g/mii modes: phy collision input. tbi mode: receive byte clock mode output. when low the e0_pma_clk0 and e0_pma_clk1 are active as half rate clocks. when high the e0_pma_clk0 is active as a 125mhz clock input. e0_ecmdt 1 to tbi mode: enable comma de tect. enables serdes to perform code group alignment upon detection of comma. e0_ewrap 1 to tbi mode: enable wrap. enables serdes to loop transmit signals to receive (loopback). e0_prbsen 1 to tbi mode: prbs enable. used to enable prbs test mode inside tbi serdes devices. e0_prbs_pass 1 i tbi mode: prbs pass indicator input (high = pass).
intel? gw80314 i/o companion chip package information datasheet 23 e0_rxclk/ e0_pma_clk0 1 i g/mii modes: receive clock from pma. tbi mode: pma receive clock 0 or 125 mhz receive clock depending on state of rbcmode. e0_txclk/ e0_pma_clk1 1 i g/mii mode: 2.5 mhz or 25 mhz transmit clock. tbi mode: pma receive clock 1. port 1 e1_tcg[3:0] 4 to all modes: transmit code group lower nibble. e1_tcg[7:4] 4 to g/mii mode: transmit code group upper nibble. tbi mode: transmit code group upper nibble. e1_tcg[8] 1 to mii mode: transmit enable. this signal is synchronous to e1_tx_clk and provides precise framing for data carri ed on e1_tcg[3:0] for the external pma. it is asserted when e1_tcg[3:0] contains valid data to be transmitted. g/mii mode: transmit enable. this signal is synchronous to gtx_clk and provides precise framing for data carri ed on e1_tcg[7:0] for the external pma. it is asserted when e1_tcg[7:0] contains valid data to be transmitted. tbi mode: transmit code group bit 8. synchronous to gtx_clk. e1_tcg[9] 1 to mii mode: transmit error. this signal is synchronous to e1_tx_clk and provides error indications. g/mii mode: transmit error. this signal is synchronous to gtx_clk and provides error indications. tbi mode: transmit code group bit 9. synchronous to gtx_clk. e1_rcg[3:0] 4 i all modes: receive code group lower nibble. this is a group of 4 signals, sourced from an external pma, that contains data aligned on nibble boundaries and are driven synchronous to the e1_clk. e1_rcg[3] is the most significant bit and e1_rcg[0] is the least significant bit. e1_rcg[7:4] 4 i g/mii mode: receive code group upper nibble this is a group of 4 signals, sourced from an external pma, that contains data aligned on byte boundaries and are driven synchronous to the e1_clk. e1_rcg[7] is most significant bit. tbi mode: receive code group upper nibble. e1_rcg[8] 1 i g/mii modes: receive data valid. this indicates that the external pma is presenting recovered and decoded nibbles on the e1_rcg signals, and that e1_clk is synchronous to the recovered data in 100 mb/s and 1000 mb/s operation. this signal encompasses the frame, starting with the start-of-frame delimiter (jk) and excl uding any end-of-frame delimiter (tr). tbi mode: transmit code group bit 8. e1_rcg[9] 1 i g/mii modes: receive error. this signal is synchronous to e1_clk/e1_pma_clk0 and provides media error indications. tbi mode: transmit code group bit 9. e1_pcrs_sdet 1 i g/mii modes: phy carrier sense indication. tbi mode: indicates signals detected. e1_pcol_rbcm 1 io g/mii modes: phy collision input. tbi mode: receive byte clock mode output. when low the e1_pma_clk0 and e1_pma_clk1 are active as half rate clocks. when high the e1_pma_clk0 is active as a 125 mhz clock input. e1_ecmdt 1 to tbi mode: enable comma dete ct. enables serdes to perform code group alignment upon detection of comma. e1_ewrap 1 to tbi mode: enable wrap. enables serdes to loop transmit signals to receive (loopback). e1_prbsen 1 to tbi mode: prbs enable. used to enable prbs test mode inside tbi serdes devices. e1_prbs_pass 1 i tbi mode: prbs pass indicator input (high = pass). table 6. gige signals (sheet 2 of 3) pin name count pin type description
intel? gw80314 i/o companion chip package information 24 datasheet 3.1.5 peripheral bus interface signals this section describes signals for the gw80314 peripheral bus. signals in this group are 3.3 v lvttl compatible. e1_rxclk/ e1_pma_clk0 1 i g/mii modes: receive clock from pma. tbi mode: pma receive clock 0 or 125 mhz receive clock depending on state of rbcmode. e1_txclk/ e1_pma_clk1 1 i g/mii mode: 2.5 mhz or 25 mhz transmit clock. tbi mode: pma receive clock 1. management interface mdc 1 o management data clock (2.5 mhz by 802.3 specification.) mdio 1 io management data i/o bidirectional pin. gigabit clocks ref125m 1 i all modes: 125 mhz reference clock input. gtx_clk 1 o all modes: 125 mhz transmit clock output. gige pin count 60 table 6. gige signals (sheet 3 of 3) pin name count pin type description table 7. peripheral bus interface signals pin name count pin type description pbi_ad[31:0] 32 io address/data bus. pbi_oe# 1 o output enable. pbi_cs#[3:0] 4 o chip selects: active low signal indicating that an external device has been selected for access. pbi_le 1 io latch enable: address latch signal to indicate when addresses are valid on the pbi_ad bus. pbi_rdy# 1 i ready input: in handshake mode, indi cates that external device is ready to commence transfer. pbi_rw 1 o read/write enable: low indicates a write access is underway. pbi pin count 40
intel? gw80314 i/o companion chip package information datasheet 25 3.1.6 p1 pci/x signals this section describes the gw80314 pci/x signals on the p1 pci/x bus. table 8. p1 pci/x signals (sheet 1 of 2) pin name count pin type description p1_ack64# 1 io acknowledge 64-bit transaction: active low signal asserted by a target to indicate its willingness to participate in a 64-bit transaction. driven by the target; sampled by the master. rescinded by the target at the end of the transaction. p1_ad[63:0] 64 io address/data bus: address and data are multiplexed over these pins providing a 64-bit address/data bus. p1_cbe#[7:0] 8 io bus command and byte enable lines: command and byte enable information is multiplexed over all eight cbe lines. p1_clk_in 1 i pci input clock: clock in for the pci/x port 1 interface used to generate fixed timing parameters. p1_clk_in can operate between 25 and 133 mhz p1_clk_out 1 o pci output clock: clock out for the pci/x port 1 interface. this is a valid clock output only when this interface is used as the controlling resource. p1_devsel# 1 io device select: an active low indication from an agent that is the target of the current transaction. driven by the target; sampled by the master. rescinded by the target at the end of the transaction. p1_frame# 1 io cycle frame for pci/x bus: an active low indication from the current bus master of the beginning and end of a tr ansaction. driven by the bus master; sampled by the selected target. rescinded by the bus master at the end of the transaction. p1_gnt#[1] 1 io grant: this is an input when an external arbiter is used and an output when the internal arbiter is used. as an input it is used by the external arbiter to grant the bus to the gw80314. as an output it is used by the internal arbiter to grant the bus to an external master. p1_gnt#[7:2] 6 to grant: these are used by the inte rnal arbiter to grant the bus to an external master p1_idsel 1 i initialization device select: used as a chip select during configuration 0 read and write transactions p1_inta# 1 io(od) interrupt a: an active low level sensitive indication of an interrupt. p1_intb# 1 io(od) interrupt b: an active low level sensitive indication of an interrupt. p1_intc# 1 io(od) interrupt c: an active low level sensitive indication of an interrupt. p1_intd# 1 io(od) interrupt b: an active low level sensitive indication of an interrupt. p1_irdy# 1 io initiator ready: an active low indication of the current bus master?s ability to complete the current data phase. driven by the master; sampled by the selected target. p1_m66en 1 i pci 66 mhz enable: controls the 33/66 mhz clock generation when in pci mode. when pulled low, it configures the pci port 1 pll clock output for 33 mhz. when pulled high, it configures the pci port 1 pll for 66 mhz operation. p1_par 1 io parity: carries even parity ac ross p1_ad[31:0] and p1_c/be[3:0]. driven by the master for the address and write data phases. driven by the target for read data phases. p1_par64 1 io parity upper dword: carries even parity across p1_ad[63:32] and p1_cbe[7:4]. driven by the master for address and write data phases. driven by the target for read data phases. p1_pcixcap[1:0] 2 i pci/x capability pin: indicates the speed and mode of pci/x interface when configured as the contro l resource (p1_rstdir = 1). p1_perr# 1 io parity error: an active low indication of a data parity error. driven by the target receiving data. rescinded by that agent at the end of the transaction.
intel? gw80314 i/o companion chip package information 26 datasheet p1_pme# 1 io(od) power management (optional interrupt pin) p1_req#[1] 1 io bus request: this is an output when an external arbiter is used and an input when the internal arbiter is used. as an input it is used by an external master to request the bus. as an output it is used by the gw80314 to request the bus. p1_req#[7:2] 6 i bus request: these signals are used by external masters to request the pci/x bus. p1_req64# 1 io request 64-bit transfer: an active low indication from the current master of its choice to perform 64-bit transactions. rescinded by the bus master at the end of the transaction. p1_rst# 1 io reset: asynchronous active low reset for pci/x interface. when the interface is the secondary side in a transparent bridge, this pin is configured as an output. p1_rstdir 1 i reset direction: 0 = p1_rst# is input and p1_clk_out is driven to 0. 1 = p1_rst# is output and p1_clk_out is generated (pci port 1 is controlling resource). p1_serr# 1 od system error: an active low indication of address parity error. p1_stop# 1 io stop: an active low indication from the target of its desire to stop the current transition. sampled by the master; rescinded by the target at the end of the transaction p1_trdy# 1 io target ready: an active low indication of the current target?s ability to complete the data phase. driven by the target; sampled by the current bus master. rescinded by the target at the end of the transaction. p1 pci/x pin count 110 table 8. p1 pci/x signals (sheet 2 of 2) pin name count pin type description
intel? gw80314 i/o companion chip package information datasheet 27 3.1.7 p2 pci/x signals this section describes the gw80314 pci/x signals on p2 pci/x bus. table 9. p2 pci/x signals (sheet 1 of 2) pin name count pin type description p2_ack64# 1 io acknowledge 64-bit transaction: active low signal asserted by a target to indicate its willingness to participate in a 64-bit transaction. driven by the target; sampled by the master. rescinded by the target at the end of the transaction. p2_ad[63:0] 64 io address/data bus: address and data are multiplexed over these pins providing a 64-bit address/data bus. p2_cbe#[7:0] 8 io bus command and byte enable lines: command and byte enable information is multiplexed over all eight cbe lines. p2_clk_in 1 i pci input clock: clock input for the pci/x port 1 interface used to generate fixed timing parameters. p2_clk_in can operate between 25 and 133 mhz. p2_clk_out 1 o pci output clock: clock out for the pci/x port 2 interface. this is a valid clock output only when this interface is used as the controlling resource. p2_devsel# 1 io device select: an active low indication from an agent that is the target of the current transaction. driven by the target; sampled by the master. rescinded by the target at the end of the transaction. p2_frame# 1 io cycle frame for pci/x bus: an active low indication from the current bus master of the beginning and end of a tr ansaction. driven by the bus master; sampled by the selected target. rescinded by the bus master at the end of the transaction. p2_gnt#[1] 1 io grant: this is an input when an external arbiter is used and an output when the internal arbiter is used. as an input it is used by the external arbiter to grant the bus to the gw80314. as an output it is used by the internal arbiter to grant the bus to an external master. p2_gnt#[7:2] 6 to grant: these are used by the inte rnal arbiter to grant the bus to an external master. p2_idsel 1 i initialization device select: used as a chip select during configuration read and write transactions. p2_inta# 1 io(od) interrupt a: an active low level sensitive indication of an interrupt. p2_intb# 1 io(od) interrupt b: an active low level sensitive indication of an interrupt. p2_intc# 1 io(od) interrupt c: an active low level sensitive indication of an interrupt. p2_intd# 1 io(od) interrupt d: an active low level sensitive indication of an interrupt. p2_irdy# 1 io initiator ready: an active low indication of the current bus master?s ability to complete the current data phase. driven by the master; sampled by the selected target. p2_m66en 1 i pci 66 mhz enable: controls 33/66 mhz clock generation when in pci mode. when pulled low, it configures the pci port 2 pll clock output for 33mhz operation. when pulled high, it configures the pci port 2 pll clock output for 66mhz operation. p2_par 1 io parity: carries even parity ac ross p2_ad[31:0] and p2_c/be[3:0]. driven by the master for the address and write data phases. driven by the target for read data phases. p2_par64 1 io parity upper dword: carries even parity across p2_ad[63:32] and p2_cbe[7:4]. driven by the master for address and write data phases. driven by the target for read data phases. p2_pcixcap[1:0] 2 i pci/x capability pin: indicates the speed and mode of pci/x interface when configured as the contro l resource (p2_rstdir = 1). p2_perr# 1 io parity error: an active low indication of a data parity error. driven by the target receiving data. rescinded by that agent at the end of the transaction.
intel? gw80314 i/o companion chip package information 28 datasheet p2_pme# 1 io(od) power management (optional interrupt pin). p2_req#[1] 1 io bus request: this is an output when an external arbiter is used and an input when the internal arbiter is used. as an input it is used by an external master to request the bus. as an output it is used by the gw80314 to request the bus. p2_req#[7:2] 6 i bus request: these signals are used by external masters to request the pci/x bus. p2_req64# 1 io request 64-bit transfer: an active low indication from the current master of its choice to perform 64-bit transactions. rescinded by the bus master at the end of the transaction. p2_rst# 1 io reset: asynchronous active low reset for pci/x interface p2_rstdir 1 i reset direction: 0 = p2_rst# is input and p2_clk_out is driven to 0. 1 = p2_rst# is output and p2_clk_out is generated (pci port 2 is controlling resource). p2_serr# 1 o(od) system error: an active low indication of address parity error. p2_stop# 1 io stop: an active low indication from the target of its desire to stop the current transition. sampled by the master; rescinded by the target at the end of the transaction p2_trdy# 1 io target ready: an active low indication of the current target?s ability to complete the data phase. driven by the target; sampled by the current bus master. rescinded by the target at the end of the transaction. p2 pci/x pin count 110 table 9. p2 pci/x signals (sheet 2 of 2) pin name count pin type description
intel? gw80314 i/o companion chip package information datasheet 29 3.1.8 p1 hot swap signals this section describes the gw80314 pci port 1 hot swap signals. 3.1.9 p2 hot swap signals this section describes the gw80314 pci port 2 hot swap signals. 3.1.10 interrupt controller signals this section describes signals for the gw80314 interrupt controller. signals in this group are 3.3 v lvttl compatible. table 10. p1 hot swap signals pin name count pin type description p1_enum# 1 io(od) system enumeration: used to notify system host that a board has been freshly inserted or extracted from the system. p1_es 1 i ejector switch: indicates the status of hot swap board ejector switch. p1_healthy# 1 i board healthy - in a cpci hot swap environment, indicates the board is ready to be released from reset and become an active agent on the pci bus. negation of p1_healthy# resets all gw80314 resources, including plls. additionally, all gw80314 outputs are tris tated when this pin is negated; some inputs and bidirectionals are inhibited. p1_hs_64en# 1 i pci/x 64-bit enable: an active low indication that a compactpci hot swap board is in a 64-bit slot. p1_led# 1 od led: controls the hot swap status led. p1 hot swap pin count 5 table 11. p2 hot swap signals pin name count pin type description p2_enum# 1 io(od) system enumeration: used to notify system host that a board has been freshly inserted or extracted from the system. p2_es 1 i ejector switch: indicates the status of hot swap board ejector switch. p2_healthy# 1 i board healthy - in a cpci hot swap environment, indicates the board is ready to be released from reset and become an active agent on the pci bus. negation of p1_healthy# resets all gw80314 resources, including plls. additionally, all gw80314 outputs are tris tated when this pin is negated; some inputs and bidirectionals are inhibited. p2_hs_64en# 1 i pci/x 64-bit enable: an active low indication that a compactpci hot swap board is in a 64-bit slot. p2_led# 1 o led: controls the hot swap status led. p2 hot swap pin count 5 table 12. interrupt controller signals pin name count pin type description int[15:8] 8 io inputs representing external, incoming interrupts. int[7:0] 8 i inputs representing external, incoming interrupts. interrupt total 16
intel? gw80314 i/o companion chip package information 30 datasheet 3.1.11 dual uart signals this section describes signals for the gw80314 dual uarts. signals in this group are 3.3 v lvttl compatible. on reset, gpio[7:0] are gw80314 outputs driven to the value 0x88h and remain driven until firmware configures. table 13. uart signals pin name count pin type description uart0 u0_rx 1 i data in: serial input data u0_tx 1 o data out: serial output data u0_cts# 1 i clear to send: when low, this indicates that the modem or data set is ready to exchange data. u0_rts# 1 o request to send: when low, this informs the modem or data set that the uart is ready to exchange data. u0_dsr#/ gpio[6] 1 io data set ready output: when low, this indicates that the modem or data set is ready to establish the communications link with the uart. this pin is multiplexed with gpio[6]. u0_dtr#/ gpio[7] 1 io data terminal ready output: when low, this informs the modem or data set that the uart is ready to establish a communications link. this pin is multiplexed with gpio[7]. u0_dcd#/ gpio[4] 1 io data carrier detect output: when low, this indicates that the data carrier has been detected by the modem or data set. this pin is multiplexed with gpio[4]. u0_ri#/ gpio[5] 1 io ring indicator output: when low, this indicates that a telephone ringing signal has been received by the modem or data set. this pin is multiplexed with gpio[5]. uart1 u1_rx 1 i data in: serial input data u1_tx 1 o data out: serial output data u1_cts# 1 i clear to send: when low, this indicates that the modem or data set is ready to exchange data. u1_rts# 1 o request to send: when low, this informs the modem or data set that the uart is ready to exchange data. u1_dsr#/ gpio[2] 1 io data set ready output: when low, this indicates that the modem or data set is ready to establish the communications link with the uart. this pin is multiplexed with gpio[2]. u1_dtr#/ gpio[3] 1 io data terminal ready output: when low, this informs the modem or data set that the uart is ready to establish a communications link. this pin is multiplexed with gpio[3]. u1_dcd#/ gpio[0] 1 io data carrier detect output: when low, this indicates that the data carrier has been detected by the modem or data set. this pin is multiplexed with gpio[0]. u1_ri#/ gpio[1] 1 io ring indicator output: when low, this indicates that a telephone ringing signal has been received by the modem or data set. this pin is multiplexed with gpio[1]. uart pin count 16
intel? gw80314 i/o companion chip package information datasheet 31 3.1.12 i 2 c signals this section describes the gw80314 i 2 c signals, which are 3.3 v lvttl compatible. 3.1.13 miscellaneous signals this section describes the gw80314 miscellaneous signals which are 3.3 v lvttl compatible. table 14. i 2 c signals pin name count pin type description i2c_sclk 1 od i 2 c serial clock output - eeprom serial clock. internally pulled high. i2c_sda 1 io(od) serial data - eeprom serial data line. this signal is internally pulled high. i2c pin count 2 table 15. miscellaneous signals pin name count pin type description pwrup_pbi_bswp (configuration pin) 1 i used during power-up to determine whether the pbi interface is operating in intel xscale ? microprocessor byte swap mode (1 - enable byte swap mode). pwrup_p1_arb (configuration pin) 1 i used during power-up to determine whet her the pci1 interface uses the internal gw80314 pci1 arbiter (1 - internal arbiter selected). pwrup_p1_prim 1 i transparent m ode: always strap low - 0. embedded mode: used in conjunction with p1_rstdir to determine the source of chip reset. pwrup_p2_arb (configuration pin) 1 i used during power-up to determine whet her the pci2 interface uses the internal gw80314 pci2 arbiter (1 - internal arbiter selected). pwrup_p2_prim 1 i transparent m ode: always strap low - 0. embedded mode: used in conjunction with p2_rstdir to determine the source of chip reset. pwrup_trans (configuration pin) 1 i used during power-up to determine whet her the p2p bridge is operating in embedded or transparent mode. 0 = embedded mode operation 1 = transparent mode operation pwrup_xs_swrst (configuration pin) 1 i controls state of software reset inside intel xscale ? microprocessor ciu block (1 - intel xscale ? interface held in reset until cleared by processor). pwrup_p1_swrst (configuration pin) 1 i controls state of software reset inside p1 pci/x block (1 - pci1 interface held in reset until cleared by processor). pwrup_p2_swrst (configuration pin) 1 i controls state of software reset inside p2 pci/x block (1 - pci2 interface held in reset until cleared by processor). pwrup_p1_byp (configuration pin) 1 i used during power up to enable p1pci pll bypass mode (1 - pci1 pll is bypassed). pwrup_p2_byp (configuration pin) 1 i used during power up to enable p2 pci pll bypass mode (1 - pci2 pll is bypassed). sfn_clk 1 i fabric clock input. sfn_rst# 1 i fabric gasket reset and general chip reset. sram_sku 1 i the sram_sku pin (aw33) is an input-only pin with an internal pull-up. when this pin is tied low, the sdram inside the intel ? gw80314 i/o companion chip is inaccessible. ?no sra m? skew parts must tie this pin low. when this pin is left floating, the device id incorrectly indicates that sdram is usable. nc_(location) 5 no connect pins (nc_j35, nc_k34, nc_l6, nc_m33, nc_n6) misc. pin count 19
intel? gw80314 i/o companion chip package information 32 datasheet 3.1.14 test signals this section describes the gw80314 signals used to support silicon or board-level testing. signals in this section are 3.3 v lvttl compatible. 3.1.15 pll power signals this section describes the gw80314 signals used to support on board plls for the various interfaces. each avcc pin supplies 3.3 v (typical) to each interface. table 16. test signals pin name count pin type description tck 1 i test clock (jtag): used to clock state information and data into and out of the device during boundary scan tms 1 i(pu) test mode select (jtag): used to control the state of the tap controller. internally pulled high. tdi 1 i(pu) test data input (jtag): used to shift data and instruction into boundary scan. internally pulled high. tdo 1 to test data output (jtag): used to shift data and instruction out of boundary scan trst# 1 i(pu) test reset (jtag): asynchronous reset for the jtag controller. this pin must be asserted low during the power-up reset sequence to ensure that the boundary scan register elements ar e configured for normal system operation. customers must assert trst# concurrently with sf_rst or p1_rst or p2_rst (depending on power- up configurations) as part of the power-up reset sequence. internally pulled high. pull-down resistor when jtag is not used. test pin count 5 table 17. pll power signals pin name count pin type description xs_pll_avcc ( v cc33 ) 1 s analog power pin for intel xscale ? microprocessor interface pll. xs_pll_avss 1 s analog ground pin for intel xscale ? microprocessor interface pll. sd_pll_avcc ( v cc33 ) 1 s analog power pin for ddr sdram interface pll. sd_pll_avss 1 s analog ground pin for ddr sdram interface pll. p1_pll_avcc ( v cc33 ) 1 s analog power pin for pci1 interface pll. p1_pll_avss 1 s analog ground pin for pci1 interface pll. p2_pll_avcc ( v cc33 ) 1 s analog power pin for pci2 interface pll. p2_pll_avss 1 s analog ground pin for pci2 interface pll. pll supply count 8
intel? gw80314 i/o companion chip package information datasheet 33 3.1.16 power supplies this section describes the gw80314 power supplies used to support both i/o interfaces and core elements. table 18. power supplies pin name pin type / count description vcc_core ( v cc12 ) s / 75 core power supply for the gw80314. vcc_pc ( v cc33 ) s / 56 i/o power supply for pci interface. vcc_sd ( v cc25 ) s / 26 i/o power supply for ddr sdram interface. vcc_xs ( v cc33 ) s / 28 i/o power supply for intel xscale ? microprocessor interface. vss_core s / 73 core ground supply for the gw80314. vss_io s / 119 i/o ground supply. vcc pin count total 185 vss pin count total 192
intel? gw80314 i/o companion chip package information 34 datasheet 3.1.17 signal pin mode behavior this section describes the gw80314 signal pin mode behavior during reset, normal operation, 32-bit pci mode, and error correction mode. table 19. signal pin mode behavior (sheet 1 of 7) pin name reset norm hold 32-bit pci 32-bit mem ecc off xs_a[15:0] vi vi ? ? ? ? xs_abort 0 vo ? ? ? ? xs_be[7:0] 0 vb ? ? ? ? xs_clk 0 vb ? ? ? ? xs_cwf / dbuswidth 0 vo ? ? ? ? xs_dq[63:0] 0 vb ? ? ? ? xs_dvalid[1:0] 0 vo ? ? ? ? xs_hold[1:0] 0 vo ? ? ? ? xs_hlda[1:0] vi vi ? ? ? ? xs_ecc[7:0] 0 vb ? ? ? ? xs_fiq[1] / pwrup_sd_byp l vo 1 ? ? ? xs_fiq[0] 0 vo ? ? ? ? xs_irq[1]/pwrup_xs_byp l vo 1 ? ? ? xs_irq[0]/pwrup_fadj l vo 1 ? ? ? xs_len[2:0] vi vi ? ? ? ? xs_reset# 0 vo ? ? ? ? sd_a[13:0] 0* vo ? ? ? ? sd_ba[1:0] 0* vo ? ? ? ? sd_cas# 1* vo ? ? ? ? sd_clk[3:0] vo vo ? ? ? ? sd_clk#[3:0] vo vo ? ? ? ? sd_clken 0* vo ? ? ? ? sd_ckfbi vi vi ? ? ? ? sd_ckfbo vo vo ? ? ? ? sd_cs#[7:0] 1* vo ? ? ? ? sd_dq[63:32] z* vb ? ? id ? notes: 1. 1 = driven to v cc 2. z = output disabled (floats) 3. 0 = driven to v ss 4. vb = acts like a valid bidirectional pin 5. id = input is disabled 6. vo = a valid output level is driven 7. vo m = a valid output level is driven (pci master) 8. vo t = a valid output level is driven (pci target) 9. h = pulled up to v cc 10.l = pulled down to v ss 11.vi = need to drive a valid input level 12.vi m = need to drive a valid input level (pci master) 13.vi t = need to drive a valid input level (pci target) 14.pd = pull-up disabled 15.* = after power fail sequence completes
intel? gw80314 i/o companion chip package information datasheet 35 sd_dq[31:0] z* vb ? ? ? ? sd_dqs[17] z* vb ? ? ? id sd_dqs/dm[16:9] z* vb ? ? id ? sd_dqs[8] z* vb ? ? ? id sd_dqs[7:0] z* vb ? ? ? ? sd_ecc z* vb ? ? ? id sd_i2c_clk h vo ? ? ? ? sd_i2c_sda h vb ? ? ? ? sd_ras# 1* vo ? ? ? ? sd_we# 1* vo ? ? ? ? sd_pwrdelay vi vi ? ? ? ? e0_tcg[9:0] vo vo ? ? ? ? e0_rcg[9:0] vi vi ? ? ? ? e0_pcrs_sdet vi vi ? ? ? ? e0_pcol_rbcm z vb ? ? ? ? e0_ecmdt z vo ? ? ? ? e0_ewrap z vo ? ? ? ? e0_prbsen z vo ? ? ? ? e0_prbs_pass vi vi ? ? ? ? e0_rxclk/e0_pma_clk0 vi vi ? ? ? ? e0_txclk/e0_pma_clk1 vi vi ? ? ? ? e1_tcg[9:0] vo vo ? ? ? ? e1_rcg[9:0] vi vi ? ? ? ? e1_pcrs_sdet vi vi ? ? ? ? e1_pcol_rbcm z vb ? ? ? ? e1_ecmdt z vo ? ? ? ? e1_ewrap z vo ? ? ? ? e1_prbsen z vo ? ? ? ? e1_prbs_pass vi vi ? ? ? ? e1_rxclk/e1_pma_clk0 vi vi ? ? ? ? table 19. signal pin mode behavior (sheet 2 of 7) pin name reset norm hold 32-bit pci 32-bit mem ecc off notes: 1. 1 = driven to v cc 2. z = output disabled (floats) 3. 0 = driven to v ss 4. vb = acts like a valid bidirectional pin 5. id = input is disabled 6. vo = a valid output level is driven 7. vo m = a valid output level is driven (pci master) 8. vo t = a valid output level is driven (pci target) 9. h = pulled up to v cc 10.l = pulled down to v ss 11.vi = need to drive a valid input level 12.vi m = need to drive a valid input level (pci master) 13.vi t = need to drive a valid input level (pci target) 14.pd = pull-up disabled 15.* = after power fail sequence completes
intel? gw80314 i/o companion chip package information 36 datasheet e1_txclk/e1_pma_clk1 vi vi ? ? ? ? mdc 0vo???? mdio z vb ? ? ? ? ref125m vi vi ? ? ? ? gtx_clk 0vo???? pbi_ad[31:0] 0 vb z ? ? ? pbi_oe# 1 vo ? ? ? ? pbi_cs#[3:0] 1 vo ? ? ? ? pbi_le 0 vo z ? ? ? pbi_rdy# vi vi ? ? ? ? pbi_rw 0 vo z ? ? ? p1_ack64# z vb ? ? ? ? p1_ad[63:32] z vb ? h ? ? p1_ad[31:0] z vb ? ? ? ? p1_cbe#[7:4] z vb ? h ? ? p1_cbe#[3:0] z vb ? ? ? ? p1_clk_in vi vi ? ? ? ? p1_clk_out 0 vo ? ? ? ? p1_devsel# z vb ? ? ? ? p1_frame# zvb???? p1_gnt#[1] z vb ? ? ? ? p1_gnt#[7:2] z vo ? ? ? ? p1_idsel vi vi ? ? ? ? p1_inta# z vo ? ? ? ? p1_intb# z vo ? ? ? ? p1_intc# z vo ? ? ? ? p1_intd# z vo ? ? ? ? p1_irdy# zvb???? p1_m66en vi vi ? ? ? ? p1_par z vb ? ? ? ? table 19. signal pin mode behavior (sheet 3 of 7) pin name reset norm hold 32-bit pci 32-bit mem ecc off notes: 1. 1 = driven to v cc 2. z = output disabled (floats) 3. 0 = driven to v ss 4. vb = acts like a valid bidirectional pin 5. id = input is disabled 6. vo = a valid output level is driven 7. vo m = a valid output level is driven (pci master) 8. vo t = a valid output level is driven (pci target) 9. h = pulled up to v cc 10.l = pulled down to v ss 11.vi = need to drive a valid input level 12.vi m = need to drive a valid input level (pci master) 13.vi t = need to drive a valid input level (pci target) 14.pd = pull-up disabled 15.* = after power fail sequence completes
intel? gw80314 i/o companion chip package information datasheet 37 p1_par64 z vb ? h ? ? p1_pcixcap[1:0] vi vi ? ? ? ? p1_perr# z vb ? ? ? ? p1_pme# z vb ? ? ? ? p1_req#[1] z vb ? ? ? ? p1_req#[7:2] vi vi ? ? ? ? p1_req64# vo m /vi t vo m /vi t ???? p1_rst# vb vb ? ? ? ? p1_rstdir vi vi ? ? ? ? p1_serr# z vb ? ? ? ? p1_stop# vo t /vi m vo t /vi m ???? p1_trdy# vo t /vi m vo t /vi m ???? p2_ack64# z vb ? ? ? ? p2_ad[63:32] z vb ? h ? ? p2_ad[31:0] z vb ? ? ? ? p2_cbe#[7:4] z vb ? h ? ? p2_cbe#[3:0 z vb ? ? ? ? p2_clk_in vi vi ? ? ? ? p2_clk_out 0 vo ? ? ? ? p2_devsel# z vb ? ? ? ? p2_frame# z vb ? ? ? ? p2_gnt#[1] z vb ? ? ? ? p2_gnt#[7:2] z vo ? ? ? ? p2_idsel vi vi ? ? ? ? p2_inta# z vo ? ? ? ? p2_intb# z vo ? ? ? ? p2_intc# z vo ? ? ? ? p2_intd# z vo ? ? ? ? p2_irdy# z vb ? ? ? ? p2_m66en vi vi ? ? ? ? table 19. signal pin mode behavior (sheet 4 of 7) pin name reset norm hold 32-bit pci 32-bit mem ecc off notes: 1. 1 = driven to v cc 2. z = output disabled (floats) 3. 0 = driven to v ss 4. vb = acts like a valid bidirectional pin 5. id = input is disabled 6. vo = a valid output level is driven 7. vo m = a valid output level is driven (pci master) 8. vo t = a valid output level is driven (pci target) 9. h = pulled up to v cc 10.l = pulled down to v ss 11.vi = need to drive a valid input level 12.vi m = need to drive a valid input level (pci master) 13.vi t = need to drive a valid input level (pci target) 14.pd = pull-up disabled 15.* = after power fail sequence completes
intel? gw80314 i/o companion chip package information 38 datasheet p2_par z vb ? ? ? ? p2_par64 z vb ? h ? ? p2_pcixcap[1:0] vi vi ? ? ? ? p2_perr# z vb ? ? ? ? p2_pme# zvb???? p2_req#[1] z vb ? ? ? ? p2_req#[7:2] vi vi ? ? ? ? p2_req64# vo m /vi t vo m /vi t ???? p2_rst# vb vb ? ? ? ? p2_rstdir vi vi ? ? ? ? p2_serr# z vb ? ? ? ? p2_stop# vo t /vi m vo t /vi m ???? p2_trdy# vo t /vi m vo t /vi m ???? p1_enum# zvb???? p1_es vi vi ? ? ? ? p1_healthy# vi vi ? ? ? ? p1_hs_64en# vi vi ? ? ? ? p1_led# z vo ? ? ? ? p2_enum# zvo???? p2_es vi vi ? ? ? ? p2_healthy# vi vi ? ? ? ? p2_hs_64en# vi vi ? ? ? ? p2_led# z vo ? ? ? ? int[15:8]/tm_mon[7:0] vi vb ? ? ? ? int[7:0] vi vi ? ? ? ? u0_rx vi vi ? ? ? ? u0_tx 0vo???? u0_cts# vi vi ? ? ? ? u0_rts# 1vi???? u0_dsr#/gpio[0] vi vb ? ? ? ? table 19. signal pin mode behavior (sheet 5 of 7) pin name reset norm hold 32-bit pci 32-bit mem ecc off notes: 1. 1 = driven to v cc 2. z = output disabled (floats) 3. 0 = driven to v ss 4. vb = acts like a valid bidirectional pin 5. id = input is disabled 6. vo = a valid output level is driven 7. vo m = a valid output level is driven (pci master) 8. vo t = a valid output level is driven (pci target) 9. h = pulled up to v cc 10.l = pulled down to v ss 11.vi = need to drive a valid input level 12.vi m = need to drive a valid input level (pci master) 13.vi t = need to drive a valid input level (pci target) 14.pd = pull-up disabled 15.* = after power fail sequence completes
intel? gw80314 i/o companion chip package information datasheet 39 u0_dtr#/gpio[1] vi vb ? ? ? ? u0_dcd#/gpio[2] vi vb ? ? ? ? u0_ri#/gpio[3] vi vb ? ? ? ? u1_rx vi vi ? ? ? ? u1_tx 0 vo ? ? ? ? u1_cts# vi vi ? ? ? ? u1_rts# 1 vi ? ? ? ? u1_dsr#/gpio[4] vi vb ? ? ? ? u1_dtr#/gpio[5] vi vb ? ? ? ? u1_dcd#/gpio[6] vi vb ? ? ? ? u1_ri#/gpio[7] vi vb ? ? ? ? i2c_sclk hvo???? i2c_sda hvb???? pwrup_pbi_bswp vi vi ? ? ? ? pwrup_p1_arb vi vi ? ? ? ? pwrup_p1_prim vi vi ? ? ? ? pwrup_p2_arb vi vi ? ? ? ? pwrup_p2_prim vi vi ? ? ? ? pwrup_trans vi vi ? ? ? ? pwrup_xs_swrst vi vi ? ? ? ? pwrup_p1_swrst vi vi ? ? ? ? pwrup_p2_swrst vi vi ? ? ? ? pwrup_p1_byp vi vi ? ? ? ? pwrup_p2_byp vi vi ? ? ? ? sf_clk vi vi ? ? ? ? table 19. signal pin mode behavior (sheet 6 of 7) pin name reset norm hold 32-bit pci 32-bit mem ecc off notes: 1. 1 = driven to v cc 2. z = output disabled (floats) 3. 0 = driven to v ss 4. vb = acts like a valid bidirectional pin 5. id = input is disabled 6. vo = a valid output level is driven 7. vo m = a valid output level is driven (pci master) 8. vo t = a valid output level is driven (pci target) 9. h = pulled up to v cc 10.l = pulled down to v ss 11.vi = need to drive a valid input level 12.vi m = need to drive a valid input level (pci master) 13.vi t = need to drive a valid input level (pci target) 14.pd = pull-up disabled 15.* = after power fail sequence completes
intel? gw80314 i/o companion chip package information 40 datasheet sf_rst# vi vi ? ? ? ? tck vi vi ? ? ? ? tms h h ? ? ? ? tdi h h ? ? ? ? tdo zvo???? trst# h h ? ? ? ? table 19. signal pin mode behavior (sheet 7 of 7) pin name reset norm hold 32-bit pci 32-bit mem ecc off notes: 1. 1 = driven to v cc 2. z = output disabled (floats) 3. 0 = driven to v ss 4. vb = acts like a valid bidirectional pin 5. id = input is disabled 6. vo = a valid output level is driven 7. vo m = a valid output level is driven (pci master) 8. vo t = a valid output level is driven (pci target) 9. h = pulled up to v cc 10.l = pulled down to v ss 11.vi = need to drive a valid input level 12.vi m = need to drive a valid input level (pci master) 13.vi t = need to drive a valid input level (pci target) 14.pd = pull-up disabled 15.* = after power fail sequence completes
intel? gw80314 i/o companion chip package information datasheet 41 3.1.18 1025-lead hsbga (heat slug ball grid array) package figure 2 shows the drawings for the 1025-lead hsb ga thermally enhanced package being used for the gw80314 device. figure 2. 1025-lead hsbga package drawing b0957-02 a c e g j l n r u w aa ac ae ag aj al an ar au aw b d f h k m p t v y ab ad af ah ak am ap at av 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 31 2 ab c ?0.25 ?0.50~?0.70(1025x) c m ?0.10 m ?a? 40.00 0.20 ball pitch: ball diameter: substrate thickness: mold thickness: 40.00 0.20 38.00 1.00 0.20(4x) 38.00 ?b? 0.60 1.17 1.00 0.56 1.00 side view 0.56 ref 1.17 ref 0.40~0.60 2.23 0.13 c 0.35 ?a? c 0.20 c 0.25 seating plane 30o typ. top view 34.50 ref heat slug ?26.5~27.5 1 a c e g j l n r u w aa ac ae ag aj al an ar au aw 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 pin #1 corner s e 4.60*45o(4x) s d c s ?0.50 s b s a ?e? 34.50 ref c s ?0.30 ?d? b d f h k m p t v y ab ad af ah ak am ap at av
intel? gw80314 i/o companion chip package information 42 datasheet figure 3. ball map - left side - top view

top view (left side) !" !" !
" ! " !" !" #$ $!" !" $ !" $!" $!" !" ! " $ %# % $ $ !" !" $!" &$!" $!" !" !" !" !" !" !" % $ % ! " !" !" ! !" &$!" $ ! " !" # !
" $!" %%# %%# !" !" %%# $!" %%# !" %%# !" %%# %%# #' !" %%# %%# % % !" !" !" ! !" #% # $ !" !" !"$ !" !" !"$ !"$ !" !" &$ !" ! " !
" #' !" %%# %%# &$!" ! " !" !" !" %$ !" !" !
" %%# !" !" !" !" ' !" !" #$ !" $ !" !" !
" !" & !"$ &$!" !" !" !" !" !" !" $ !" %%# #% #$ #$ #$ % %% !" !" ! " !" !
" !" % ! " #$ % % !" % %% !" %%# %%# !" ! "$ %%# !"$ %%# !
" %%# !" %%# !" %%# % $ !
" ! " %%# %%# !" !
" !" %% % $ $ !" !" ! " !" $ &$!" $!" ! " !" !
" !" $!" $ %%# !" %%# !" # $ !"$ !" !" !" %% % &!" !" !" !" %$ !" % &!" % &!" % #$ !" %%# $ % &!" % &%!" % $ !
" !" ! " $ % &!" %%# % % $ !" %%# $!" % &!" % &! " % &!" % !" !" !" !" % &!" % &%!" % &!" % !" !" !" %%# $!" %%# % &!" % &!" % ! " !
" $!" !" !" % &%!" % &!" % %% %% %% %% %% %% !" !" $!" %%# $ % &!" % &!" % &!" % %% %% %% %% %% $ &$!" !" $!" %%# % ! " % &!" % &%!" % %% %% %% %% %% %% &$!" &$!" !" %%# !" !" % !" % &!" %%# % %% %% %% %% %% %% %% $! " $!" !" &$!" % &! " % &%! " % !" % &!" % % %% %% %% %% %% %% %% %% %% $!" !" $!" %%# $!" !" !" % &!" % &%!" % % &%! " % &! " % &!" % &!" % %$ % %$!" % %$!" % $ % !" % !" % !" %%# %%# !" # !" %%# % &!" % %%# % &!" % &!" %%# % %$!" % %$!" %%# % %$ % $!" %%# !" %%# %%# %%# ! %$ #$ !
" !" %%# %%# %%# %%# %%# %%# % % % %%# % % &%!" % &!
" % &!" % &!" % &!
" % &!" % &!
" % &%!" % &%!" % &! " % &!" % !" % !" %% %% %% %% %% %% %% ! " &$ %!" %!" % &%!
" %%# $!" &$! " & !"$ $! " %%# !" # !" %$ %%# $ %%# %# %%# !" %%# $!" %%# !" %%# !
" !" !"
intel? gw80314 i/o companion chip package information datasheet 43 figure 4. ball map - right side - top view

top view (right side) ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! "# "# "# "# "# "# "# "
# "# "# $"# % $"
# % "#& " #& "#& "#& %! "#& "#& %! "# "# %! " # "# %! "#& "#& %! ! % "# %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! %! $"# $"# % $"# $"# $"# $"# $"# $"# $"
# $"# $"# $"
# % "# % " # '% "# $"# $"# %! $"# $"# %! %! % "# % "# % "# % "
# % "#& % "# $"# $"# $"# $"# %! %! %! "# "# $ "# $"# $"# $"# $"# % "# % % "
# % "# % "# % "# %! $"# $" # $"# $"# %! "# $"# %! $"# $" # %! $"# $"# %! % "# % "#& % "# % "#& % " # % "# % " ( ( ( ( ( ( ( ( ( % % "#& % "# % "# ! ! ! ! ! % "# % "# % "# % "# % "
# % !& ( $"
# ( $"# ( ( $"# % "# % & ( % "# %! ( $"# ( $"# ( % "# ( $"# ( $"# ( $"# ( % "# %! ( $"# ( $"
# ( $"# ( $"# ( % " # % "# ( $" # ( $"# ( $" # ( $"# ( $"# ( $"# ( $"# ( $"# ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( %! %! %! ( $"# ( $"# ( $"# ( $"# ( $"# ( $"# ( $"# ( $"# ( $"# ( $"# ( $"
# ( $" # ( $"# ( $"# ( $"# ( $"# ( $"# ( "# ( "# ( " # ( "# ( "# ( "#& ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( " # ( "# ( !"# ( !"# ( "# ( "# ( "# ( "# ( %"# ( %"# ( $"# ( $"# ( $" # ( $"# ( $"# ( $"
# ( $"# ( $"# ( $"# %! %! ( ( "
# & & & ( & %& % ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( "# ( $"# ( $"# ( $"# ( $"# ( $"
# ( $"# ( %$"# ( %$"# ( %$"# ( %$"# ( $"# ( $"# & & ( $"# ( $"# & & ( $" # ( $"# ( $"
# ( $"# ( $" # ( $"# ( "# ( " # ( "# ( ! ( & & ( %"# %! %! %! %! %! %! %! %! ( ( % %"# %"# %"# ! % %"# %"# %"
# %" # % %"# %"# ! ! ! ! ! %"# %"# %"# %"# %"# % %"# ! % % & %! %! %! & "# %! "# "# "# %( "# ( & % & "# %( "# "#& "# %! " # $" #& " #& "# $"#& "# "# "# "# "
# %! %! "# "
# "# " # "# "# "# "# "# "# "# ( $"# ( $"#
intel? gw80314 i/o companion chip package information 44 datasheet table 20. 1025-lead hsbga package ? alphabetical ball listing table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 1 of 30) ball signal name a3 e0_ecmdt a4 e0_tcg[5] a5 e0_tcg[3] a6 sd_dq[63] a7 sd_dqs[6] a8 sd_vref a9 sd_dqs[7] a10 sd_dq[57] a11 sd_dq[60] a12 sd_dq[46] a13 sd_cas# a14 sd_cs#[0] a15 sd_cs#[2] a16 sd_we# a17 sd_ba[0] a18 sd_clk[3] a19 sd_ba[1] a20 sd_a[0] a21 sd_clk[0] a22 sd_a[1] a23 sd_clk[1] a24 sd_clk[2] a25 sd_a[2] a26 sd_a[4] a27 sd_a[5] a28 sd_a[8] a29 sd_a[9] a30 sd_a[12] a31 sd_dq[1] a32 sd_i2c_sda a33 sd_dq[8] a34 sd_ckfbi a35 sd_cs#[4] a36 sd_cs#[7] a37 sd_cs#[6] b2 vss_io b3 vss_io b4 e0_tcg[1] b5 mdio b6 e0_tcg[9] b7 vss_io b8 sd_dq[62] b9 sd_clken b10 vss_io b11 sd_dq[56] b12 sd_dq[43] b13 vss_io b14 sd_cs#[1] b15 sd_cs#[3] b16 vss_io b17 sd_ras# b18 sd_clk#[3] b19 vss_io b20 sd_a[10] b21 sd_clk#[0] b22 vss_io b23 sd_clk#[1] b24 sd_clk#[2] b25 vss_io b26 sd_a[3] b27 sd_a[6] b28 vss_io b29 sd_a[7] b30 sd_a[11] b31 vss_io b32 sd_a[13] b33 sd_cs#[5] b34 vss_io table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 2 of 30) ball signal name b35 sd_ckfbo b36 pbi_ad[29] b37 vss_io b38 vss_io c1 e0_rcg[3] c2 vss_io c3 vss_io c4 e0_pma_clk1 c5 mdc c6 e0_prbsen c7 sd_dqs[15] c8 sd_dq[58] c9 sd_dq[53] c10 sd_dq[49] c11 sd_dq[48] c12 sd_dq[35] c13 sd_dq[38] c14 sd_dqs[14] c15 sd_dqs[4] c16 sd_dq[37] c17 sd_dq[32] c18 sd_ecc[3] c19 sd_ecc[2] c20 sd_dqs[8] c21 sd_dq[26] c22 sd_dq[28] c23 sd_dq[25] c24 sd_dq[11] c25 sd_dq[18] c26 sd_dqs[2] c27 sd_dq[21] c28 sd_dq[20] c29 sd_dq[2] c30 sd_dq[6] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 3 of 30) ball signal name
intel? gw80314 i/o companion chip package information datasheet 45 c31 sd_dqs[9] c32 sd_i2c_clk c33 sd_pwrdelay c34 sd_dq[4] c35 pbi_ad[31] c36 pbi_ad[27] c37 vss_io c38 vss_io c39 pbi_ad[24] d1 e0_pcol_rbcm d2 e0_tcg[7] d3 e0_pcrs_sdet d4 vss_io d5 e0_prbs_pass d6 e0_tcg[2] d7 e0_tcg[8] d8 sd_dq[52] d9 sd_dq[54] d10 sd_dq[55] d11 sd_dq[50] d12 sd_dq[51] d13 sd_dq[39] d14 vss_io d15 sd_dqs[13] d16 sd_dq[33] d17 vss_io d18 sd_ecc[6] d19 sd_dq[27] d20 vss_io d21 sd_dqs[12] d22 sd_dq[29] d23 vss_io d24 sd_dq[24] d25 sd_dq[10] d26 vss_io table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 4 of 30) ball signal name d27 sd_dqs[10] d28 sd_dq[13] d29 vss_io d30 sd_dq[9] d31 sd_dq[0] d32 sd_pll_avss d33 pbi_ad[4] d34 pbi_cs#[3] d35 pbi_ad[28] d36 vss_io d37 pbi_ad[23] d38 pbi_ad[25] d39 pbi_ad[19] e1 e0_rcg[1] e2 e0_ewrap e3 e0_tcg[4] e4 e0_tcg[0] e5 e0_rcg[0] e6 vss_io e7 e1_pcol_rbcm e8 vss_io e9 sd_dq[59] e10 sd_dqs[16] e11 vss_io e12 sd_dq[47] e13 sd_dqs[5] e14 sd_dq[34] e15 sd_dq[45] e16 sd_dq[44] e17 sd_ecc[7] e18 sd_dq[31] e19 sd_dqs[17] e20 sd_ecc[1] e21 sd_ecc[5] e22 sd_ecc[4] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 5 of 30) ball signal name e23 sd_dq[19] e24 sd_dq[22] e25 sd_dq[15] e26 sd_dq[14] e27 sd_dq[16] e28 sd_dq[3] e29 sd_dqs[0] e30 sd_dq[7] e31 sd_dq[5] e32 vss_io e33 pbi_ad[26] e34 pbi_ad[21] e35 vss_io e36 pbi_ad[22] e37 pbi_ad[18] e38 pbi_ad[20] e39 vss_io f1 e0_rcg[4] f2 e0_rcg[5] f3 e1_tcg[5] f4 e0_rcg[6] f5 e0_rcg[2] f6 vcc_pc f7 vcc_core f8 e0_tcg[6] f9 vcc_sd f10 vcc_sd f11 vcc_sd f12 sd_dq[61] f13 sd_dq[42] f14 sd_dq[41] f15 vss_io f16 sd_dq[40] f17 sd_dq[36] f18 vss_io table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 6 of 30) ball signal name
intel? gw80314 i/o companion chip package information 46 datasheet f19 sd_dq[30] f20 sd_dqs[3] f21 vss_io f22 sd_ecc[0] f23 sd_dq[23] f24 vss_io f25 sd_dqs[11] f26 sd_dq[17] f27 vss_io f28 sd_dqs[1] f29 sd_dq[12] f30 vss_io f31 vcc_sd f32 pbi_ad[30] f33 vcc_xs f34 vcc_xs f35 pbi_cs#[0] f36 pbi_ad[15] f37 pbi_cs#[1] f38 pbi_rw f39 pbi_ad[17] g1 e0_rcg[8] g2 e0_rcg[9] g3 vss_io g4 e1_tcg[9] g5 e0_pma_clk0 g6 vcc_pc g7 vcc_core g8 vcc_core g9 vcc_sd g10 vcc_sd g11 vcc_sd g12 vcc_sd g13 vcc_sd g14 vcc_sd table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 7 of 30) ball signal name g15 vcc_sd g16 vcc_sd g17 vcc_sd g18 vcc_sd g19 vcc_sd g20 vcc_sd g21 vcc_sd g22 vcc_sd g23 vcc_sd g24 vcc_sd g25 vcc_sd g26 vcc_sd g27 vcc_sd g28 vcc_sd g29 vcc_sd g30 sd_pll_avcc g31 vcc_sd g32 pbi_le g33 vcc_xs g34 vcc_xs g35 pbi_cs#[2] g36 pbi_ad[14] g37 vss_io g38 pbi_ad[16] g39 pbi_ad[13] h1 e0_rcg[7] h2 e1_tcg[3] h3 e1_tcg[4] h4 e1_tcg[1] h5 e1_tcg[7] h6 vcc_pc h7 vcc_pc h8 vcc_core h9 vcc_core h10 vcc_core table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 8 of 30) ball signal name h30 vcc_core h31 vcc_core h32 vcc_core h33 vcc_xs h34 vcc_xs h35 pbi_ad[9] h36 pbi_ad[10] h37 pbi_ad[5] h38 pbi_ad[12] h39 pbi_ad[11] j1 e1_tcg[2] j2 e1_pma_clk1 j3 e1_rcg[2] j4 e1_tcg[8] j5 e1_tcg[0] j6 vcc_pc j7 vcc_core j8 vcc_core j32 vcc_core j33 vcc_xs j34 vcc_xs j35 nc_j35 j36 pbi_oe# j37 pbi_ad[8] j38 xs_dq[48] j39 vss_io k1 e1_tcg[6] k2 e1_ewrap k3 vss_io k4 ref125m k5 e1_rcg[5] k6 vcc_pc k7 vcc_core k8 vcc_core k32 vcc_core table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 9 of 30) ball signal name
intel? gw80314 i/o companion chip package information datasheet 47 k33 vcc_xs k34 nc_k34 k35 pbi_rdy# k36 pbi_ad[0] k37 xs_dq[49] k38 xs_clk k39 xs_dq[51] l1 p2_intd# l2 e1_rcg[1] l3 e1_rcg[0] l4 gtx_clk l5 e1_prbsen l6 nc_l6 l7 vcc_core l33 xs_pll_avcc l34 pbi_ad[2] l35 vss_io l36 xs_dq[50] l37 xs_dq[52] l38 xs_dq[20] l39 xs_dq[53] m1 p2_gnt#[1] m2 p2_req#[1] m3 e1_pma_clk0 m4 e1_rcg[4] m5 e1_rcg[7] m6 vss_io m7 vcc_pc m33 nc_m33 m34 xs_pll_avss m35 pbi_ad[3] m36 xs_dq[55] m37 xs_dq[54] m38 vss_io m39 xs_dq[23] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 10 of 30) ball signal name n1 p2_intb# n2 vss_io n3 e1_pcrs_sdet n4 e1_rcg[3] n5 e1_prbs_pass n6 nc_n6 n7 vcc_pc n33 vcc_xs n34 pbi_ad[6] n35 vss_io n36 xs_dq[19] n37 xs_dq[18] n38 xs_dq[16] n39 xs_dq[22] p1 p2_ad[31] p2 p2_rst# p3 p2_inta# p4 e1_ecmdt p5 e1_rcg[8] p6 e1_rcg[6] p7 vcc_pc p33 vcc_xs p34 pbi_ad[7] p35 pbi_ad[1] p36 xs_dq[17] p37 xs_dq[21] p38 vss_io p39 xs_dq[47] r1 p2_ad[26] r2 p2_healthy# r3 p2_idsel r4 p2_ad[30] r5 vss_io r6 e1_rcg[9] r7 vcc_pc table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 11 of 30) ball signal name r15 vss_core r16 vcc_core r17 vss_core r18 vcc_core r19 vss_core r20 vcc_core r21 vss_core r22 vcc_core r23 vss_core r24 vcc_core r25 vss_core r33 vcc_xs r34 xs_dq[45] r35 vss_io r36 xs_dq[43] r37 xs_dq[46] r38 xs_dq[40] r39 xs_dq[44] t1 p2_pme# t2 p2_ad[27] t3 p2_ad[28] t4 p2_ad[24] t5 p2_clk_in t6 p2_pll_avss t7 vcc_pc t15 vcc_core t16 vss_core t17 vcc_core t18 vss_core t19 vcc_core t20 vss_core t21 vcc_core t22 vss_core t23 vcc_core t24 vss_core table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 12 of 30) ball signal name
intel? gw80314 i/o companion chip package information 48 datasheet t25 vcc_core t33 vcc_xs t34 xs_dq[41] t35 xs_dq[10] t36 xs_dq[42] t37 xs_dq[14] t38 vss_io t39 xs_dq[15] u1 p2_ad[21] u2 vss_io u3 p2_intc# u4 p2_irdy# u5 vss_io u6 p2_clk_out u7 vcc_pc u15 vss_core u16 vcc_core u17 vss_core u18 vcc_core u19 vss_core u20 vcc_core u21 vss_core u22 vcc_core u23 vss_core u24 vcc_core u25 vss_core u33 vcc_xs u34 xs_dq[13] u35 vss_io u36 xs_dq[11] u37 xs_dq[9] u38 xs_dq[39] u39 xs_dq[12] v1 p2_cbe#[3] v2 p2_cbe#[1] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 13 of 30) ball signal name v3 p2_ad[25] v4 p2_ad[29] v5 p2_ad[23] v6 p2_pll_avcc v7 vcc_pc v15 vcc_core v16 vss_core v17 vcc_core v18 vss_core v19 vss_core v20 vss_core v21 vss_core v22 vss_core v23 vcc_core v24 vss_core v25 vcc_core v33 vcc_xs v34 xs_dq[8] v35 xs_dq[38] v36 xs_dq[34] v37 xs_dq[33] v38 vss_io v39 xs_dq[36] w1 p2_ad[22] w2 p2_serr# w3 p2_ad[20] w4 p2_ad[18] w5 vss_io w6 p2_devsel# w7 vcc_pc w15 vss_core w16 vcc_core w17 vss_core w18 vss_core w19 vss_core table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 14 of 30) ball signal name w20 vss_core w21 vss_core w22 vss_core w23 vss_core w24 vcc_core w25 vss_core w33 vcc_xs w34 xs_dq[37] w35 vss_io w36 xs_dq[35] w37 xs_dq[7] w38 xs_dq[3] w39 xs_dq[32] y1 p2_cbe#[2] y2 vss_io y3 p2_ad[19] y4 p2_frame# y5 p2_ad[15] y6 p2_trdy# y7 vcc_pc y15 vcc_core y16 vss_core y17 vcc_core y18 vss_core y19 vss_core y20 vss_core y21 vss_core y22 vss_core y23 vcc_core y24 vss_core y25 vcc_core y33 vcc_xs y34 xs_dq[6] y35 xs_dq[0] y36 xs_dq[2] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 15 of 30) ball signal name
intel? gw80314 i/o companion chip package information datasheet 49 y37 xs_dq[1] y38 vss_io y39 xs_dq[4] aa1 p2_ad[16] aa2 p2_ad[17] aa3 p2_perr# aa4 p2_par aa5 p2_rstdir aa6 p2_stop# aa7 vcc_pc aa15 vss_core aa16 vcc_core aa17 vss_core aa18 vss_core aa19 vss_core aa20 vss_core aa21 vss_core aa22 vss_core aa23 vss_core aa24 vcc_core aa25 vss_core aa33 vcc_xs aa34 xs_dq[5] aa35 vss_io aa36 xs_dvalid[0] aa37 xs_ecc[2] aa38 xs_ecc[0] aa39 xs_ecc[1] ab1 p2_ack64# ab2 p2_ad[12] ab3 p2_ad[13] ab4 p2_ad[9] ab5 vss_io ab6 p2_ad[14] ab7 vcc_pc table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 16 of 30) ball signal name ab15 vcc_core ab16 vss_core ab17 vcc_core ab18 vss_core ab19 vss_core ab20 vss_core ab21 vss_core ab22 vss_core ab23 vcc_core ab24 vss_core ab25 vcc_core ab33 vcc_xs ab34 xs_dvalid[1] ab35 xs_ecc[3] ab36 xs_ecc[5] ab37 xs_ecc[7] ab38 vss_io ab39 xs_ecc[6] ac1 p2_ad[10] ac2 vss_io ac3 p2_cbe#[0] ac4 p2_ad[3] ac5 p2_ad[8] ac6 p2_ad[11] ac7 vcc_pc ac15 vss_core ac16 vcc_core ac17 vss_core ac18 vcc_core ac19 vss_core ac20 vcc_core ac21 vss_core ac22 vcc_core ac23 vss_core ac24 vcc_core table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 17 of 30) ball signal name ac25 vss_core ac33 vcc_xs ac34 xs_ecc[4] ac35 vss_io ac36 xs_be[0] ac37 xs_be[2] ac38 xs_be[5] ac39 xs_be[3] ad1 p2_ad[5] ad2 p2_m66en ad3 p2_ad[6] ad4 p2_ad[4] ad5 p2_cbe#[7] ad6 p2_ad[7] ad7 vcc_pc ad15 vcc_core ad16 vss_core ad17 vcc_core ad18 vss_core ad19 vcc_core ad20 vss_core ad21 vcc_core ad22 vss_core ad23 vcc_core ad24 vss_core ad25 vcc_core ad33 vcc_xs ad34 xs_be[1] ad35 xs_len[2] ad36 xs_len[0] ad37 xs_len[1] ad38 vss_io ad39 xs_be[4] ae1 p2_cbe#[6] ae2 p2_ad[1] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 18 of 30) ball signal name
intel? gw80314 i/o companion chip package information 50 datasheet ae3 p2_ad[0] ae4 p2_req#[3] ae5 vss_io ae6 p2_ad[2] ae7 vcc_pc ae15 vss_core ae16 vcc_core ae17 vss_core ae18 vcc_core ae19 vss_core ae20 vcc_core ae21 vss_core ae22 vcc_core ae23 vss_core ae24 vcc_core ae25 vss_core ae33 vcc_xs ae34 xs_be[6] ae35 vss_io ae36 xs_be[7] ae37 xs_cwf ae38 xs_hlda[1] ae39 xs_hold[0] af1 p2_req#[4] af2 vss_io af3 p2_gnt#[2] af4 p2_req#[5] af5 p2_gnt#[4] af6 p2_enum# af7 vcc_pc af33 vcc_xs af34 xs_abort af35 xs_a[13] af36 xs_a[4] af37 xs_a[8] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 19 of 30) ball signal name af38 vss_io af39 xs_hold[1] ag1 p2_cbe#[4] ag2 p2_gnt#[5] ag3 p2_gnt#[3] ag4 p2_ad[61] ag5 vss_io ag6 p2_req#[2] ag7 vcc_pc ag33 vcc_xs ag34 xs_hlda[0] ag35 vss_io ag36 xs_a[12] ag37 xs_a[3] ag38 xs_a[1] ag39 xs_a[2] ah1 p2_ad[59] ah2 vss_io ah3 p2_ad[63] ah4 p2_ad[62] ah5 p2_ad[58] ah6 p2_par64 ah7 vcc_pc ah33 vcc_xs ah34 xs_a[0] ah35 xs_a[11] ah36 xs_a[14] ah37 xs_a[6] ah38 vss_io ah39 xs_a[7] aj1 p2_ad[55] aj2 p2_ad[60] aj3 p2_ad[56] aj4 p2_ad[53] aj5 vss_io table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 20 of 30) ball signal name aj6 p2_cbe#[5] aj7 vcc_pc aj33 vcc_xs aj34 xs_a[5] aj35 vss_io aj36 xs_a[10] aj37 xs_dq[56] aj38 xs_dq[59] aj39 xs_a[15] ak1 p2_ad[50] ak2 vss_io ak3 p2_req64# ak4 p2_ad[54] ak5 p2_ad[49] ak6 p2_ad[57] ak7 vcc_pc ak8 vcc_core ak32 vcc_core ak33 vcc_xs ak34 xs_a[9] ak35 xs_dq[60] ak36 xs_dq[57] ak37 xs_dq[61] ak38 vss_io ak39 xs_dq[62] al1 p2_ad[46] al2 p2_ad[51] al3 p2_ad[44] al4 p2_ad[43] al5 vss_io al6 p2_ad[52] al7 vcc_pc al8 vcc_core al32 vcc_core al33 vcc_pc table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 21 of 30) ball signal name
intel? gw80314 i/o companion chip package information datasheet 51 al34 u1_dtr# al35 vss_io al36 xs_dq[58] al37 xs_dq[30] al38 xs_dq[27] al39 xs_dq[29] am1 p2_ad[45] am2 vss_io am3 p2_ad[47] am4 p2_ad[40] am5 p2_ad[39] am6 p2_ad[48] am7 vcc_pc am8 vcc_core am9 vcc_core am10 vcc_core am30 vcc_core am31 vcc_core am32 vcc_core am33 vcc_pc am34 u0_dcd# am35 u0_dtr# am36 xs_dq[63] am37 xs_dq[31] am38 vss_io am39 xs_dq[28] an1 p2_ad[37] an2 p2_ad[41] an3 p2_ad[35] an4 p2_led# an5 vss_io an6 p2_ad[42] an7 vss_io an8 vcc_pc an9 vcc_pc table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 22 of 30) ball signal name an10 vcc_pc an11 vcc_pc an12 vcc_pc an13 vcc_pc an14 vcc_pc an15 vcc_pc an16 vcc_pc an17 vcc_pc an18 vcc_pc an19 vcc_pc an20 vcc_pc an21 vcc_pc an22 vcc_pc an23 vcc_pc an24 vcc_pc an25 vcc_pc an26 vcc_pc an27 vcc_pc an28 vcc_pc an29 vcc_core an30 vcc_pc an31 vcc_pc an32 vcc_pc an33 vcc_pc an34 u1_dsr# an35 vss_io an36 u0_dsr# an37 xs_dq[25] an38 xs_dq[24] an39 xs_dq[26] ap1 p2_ad[34] ap2 vss_io ap3 p2_ad[38] ap4 p2_ad[32] ap5 p2_ad[33] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 23 of 30) ball signal name ap6 p2_ad[36] ap7 p1_pll_avss ap8 p1_clk_out ap9 p1_pll_avcc ap10 p1_trdy# ap11 p1_stop# ap12 p1_ad[14] ap13 p1_ad[11] ap14 p1_ad[7] ap15 p1_ad[2] ap16 p1_enum# ap17 p1_req#[4] ap18 p1_par64 ap19 p1_cbe#[5] ap20 p1_ad[57] ap21 p1_ad[52] ap22 p1_ad[48] ap23 p1_ad[42] ap24 p1_req#[7] ap25 sf_rst# ap26 pwrup_p1_arb ap27 pwrup_trans ap28 tdo ap29 vcc_pc ap30 vcc_pc ap31 vcc_pc ap32 int[5] ap33 vss_io ap34 vss_io ap35 u0_rx ap36 u1_rx ap37 u1_cts# ap38 xs_irq[1] ap39 xs_irq[0] ar1 p2_gnt#[6] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 24 of 30) ball signal name
intel? gw80314 i/o companion chip package information 52 datasheet ar2 p2_req#[7] ar3 p2_req#[6] ar4 p2_gnt#[7] ar5 vss_io ar6 p1_ad[29] ar7 p1_clk_in ar8 p1_ad[23] ar9 p1_devsel# ar10 vss_io ar11 p1_frame# ar12 vss_io ar13 p1_rstdir ar14 vss_io ar15 p1_ad[3] ar16 vss_io ar17 p1_gnt#[4] ar18 vss_io ar19 p1_ad[61] ar20 vss_io ar21 p1_ad[53] ar22 vss_io ar23 p1_ad[43] ar24 vss_io ar25 pwrup_p1_prim ar26 pwrup_p1_swrst ar27 trst# ar28 vss_io ar29 nc ar30 int[1] ar31 nc ar32 int[11] ar33 nc ar34 i2c_sda ar35 u0_tx ar36 u0_cts# table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 25 of 30) ball signal name ar37 u0_rts# ar38 xs_fiq[1] ar39 xs_fiq[0] at1 p2_hs_64en# at2 p2_pcixcap[1] at3 p2_pcixcap[0] at4 vss_io at5 p1_rst# at6 p1_gnt#[1] at7 p1_ad[30] at8 p1_ad[24] at9 p1_irdy# at10 p1_ad[18] at11 p1_par at12 p1_ad[15] at13 p1_ad[9] at14 p1_ad[8] at15 p1_ad[4] at16 p1_req#[2] at17 p1_req#[5] at18 p1_cbe#[7] at19 p1_ad[62] at20 p1_ad[58] at21 p1_ad[54] at22 p1_ad[49] at23 p1_ad[44] at24 p1_gnt#[7] at25 p1_gnt#[6] at26 p1_led# at27 p1_hs_64en# at28 tms at29 tck at30 nc at31 nc at32 nc table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 26 of 30) ball signal name at33 int[7] at34 int[14] at35 i2c_sclk at36 vss_io at37 u1_rts# at38 u0_ri# at39 xs_reset# au1 p2_es au2 vss_io au3 vss_io au4 p1_idsel au5 p1_ad[28] au6 p1_healthy# au7 p1_intc# au8 p1_ad[25] au9 p1_ad[20] au10 p1_ad[19] au11 p1_ad[12] au12 p1_ad[13] au13 p1_ad[6] au14 p1_cbe#[0] au15 p1_gnt#[5] au16 p1_ad[0] au17 p1_ad[63] au18 p1_gnt#[3] au19 p1_cbe#[4] au20 p1_ad[56] au21 p1_ad[46] au22 p1_ad[47] au23 p1_ad[38] au24 p1_ad[40] au25 p1_ad[34] au26 p1_ad[35] au27 p1_es au28 p1_ad[32] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 27 of 30) ball signal name
intel? gw80314 i/o companion chip package information datasheet 53 au29 pwrup_p2_prim au30 tdi au31 int[2] au32 vss_io au33 int[6] au34 int[13] au35 int[15] au36 pwrup_p2_byp au37 vss_io au38 vss_io au39 u1_dcd# av2 vss_io av3 vss_io av4 p1_intd# av5 p1_ad[27] av6 vss_io av7 p1_cbe#[1] av8 p1_serr# av9 vss_io av10 p1_ad[17] av11 vss_io av12 p1_m66en av13 vss_io av14 p1_ad[1] av15 vss_io av16 p1_gnt#[2] av17 vss_io av18 p1_ad[60] av19 vss_io av20 p1_ad[51] av21 vss_io av22 p1_ad[41] av23 vss_io av24 p1_req#[6] av25 vss_io table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 28 of 30) ball signal name av26 p1_pcixcap[0] av27 p1_ad[33] av28 p1_ad[39] av29 vss_io av30 int[0] av31 int[3] av32 pwrup_p1_byp av33 int[10] av34 int[8] av35 int[12] av36 u1_tx av37 vss_io av38 vss_io aw3 p1_req#[1] aw4 p1_inta# aw5 p1_intb# aw6 p1_ad[21] aw7 p1_ad[31] aw8 p1_ad[26] aw9 p1_pme# aw10 p1_perr# aw11 p1_cbe#[3] aw12 p1_ad[22] aw13 p1_cbe#[2] aw14 p1_ad[16] aw15 p1_ack64# aw16 p1_ad[10] aw17 p1_ad[5] aw18 p1_req#[3] aw19 p1_cbe#[6] aw20 p1_req64# aw21 p1_ad[59] aw22 p1_ad[55] aw23 p1_ad[50] aw24 p1_ad[45] table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 29 of 30) ball signal name aw25 p1_ad[37] aw26 pwrup_p2_swrst aw27 p1_pcixcap[1] aw28 pwrup_xs_swrst aw29 pwrup_pbi_bswp aw30 p1_ad[36] aw31 sf_clk aw32 int[9] aw33 sram_sku aw34 pwrup_p2_arb aw35 nc aw36 int[4] aw37 u1_ri# table 20 1025-lead hsbga package ? alphabetical ball listing (sheet 30 of 30) ball signal name
intel? gw80314 i/o companion chip package information 54 datasheet table 21. 1025-lead hsbga package ? alphabetical signal listing table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 1 of 30) signal name ball e0_ecmdt a3 e0_ewrap e2 e0_pcol_rbcm d1 e0_pcrs_sdet d3 e0_pma_clk0 g5 e0_pma_clk1 c4 e0_prbs_pass d5 e0_prbsen c6 e0_rcg[0] e5 e0_rcg[1] e1 e0_rcg[2] f5 e0_rcg[3] c1 e0_rcg[4] f1 e0_rcg[5] f2 e0_rcg[6] f4 e0_rcg[7] h1 e0_rcg[8] g1 e0_rcg[9] g2 e0_tcg[0] e4 e0_tcg[1] b4 e0_tcg[2] d6 e0_tcg[3] a5 e0_tcg[4] e3 e0_tcg[5] a4 e0_tcg[6] f8 e0_tcg[7] d2 e0_tcg[8] d7 e0_tcg[9] b6 e1_ecmdt p4 e1_ewrap k2 e1_pcol_rbcm e7 e1_pcrs_sdet n3 e1_pma_clk0 m3 e1_pma_clk1 j2 e1_prbs_pass n5 e1_prbsen l5 e1_rcg[0] l3 e1_rcg[1] l2 e1_rcg[2] j3 e1_rcg[3] n4 e1_rcg[4] m4 e1_rcg[5] k5 e1_rcg[6] p6 e1_rcg[7] m5 e1_rcg[8] p5 e1_rcg[9] r6 e1_tcg[0] j5 e1_tcg[1] h4 e1_tcg[2] j1 e1_tcg[3] h2 e1_tcg[4] h3 e1_tcg[5] f3 e1_tcg[6] k1 e1_tcg[7] h5 e1_tcg[8] j4 e1_tcg[9] g4 gtx_clk l4 i2c_sclk at35 i2c_sda ar34 int[0] av30 int[1] ar30 int[2] au31 int[3] av31 int[4] aw36 int[5] ap32 int[6] au33 int[7] at33 int[8] av34 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 2 of 30) signal name ball int[9] aw32 int[10] av33 int[11] ar32 int[12] av35 int[13] au34 int[14] at34 int[15] au35 mdc c5 mdio b5 nc ar29 nc ar31 nc ar33 nc at30 nc at31 nc at32 nc aw35 nc_j35 j35 nc_k34 k34 nc_l6 l6 nc_m33 m33 nc_n6 n6 p1_ack64# aw15 p1_ad[0] au16 p1_ad[1] av14 p1_ad[2] ap15 p1_ad[3] ar15 p1_ad[4] at15 p1_ad[5] aw17 p1_ad[6] au13 p1_ad[7] ap14 p1_ad[8] at14 p1_ad[9] at13 p1_ad[10] aw16 p1_ad[11] ap13 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 3 of 30) signal name ball
intel? gw80314 i/o companion chip package information datasheet 55 p1_ad[12] au11 p1_ad[13] au12 p1_ad[14] ap12 p1_ad[15] at12 p1_ad[16] aw14 p1_ad[17] av10 p1_ad[18] at10 p1_ad[19] au10 p1_ad[20] au9 p1_ad[21] aw6 p1_ad[22] aw12 p1_ad[23] ar8 p1_ad[24] at8 p1_ad[25] au8 p1_ad[26] aw8 p1_ad[27] av5 p1_ad[28] au5 p1_ad[29] ar6 p1_ad[30] at7 p1_ad[31] aw7 p1_ad[32] au28 p1_ad[33] av27 p1_ad[34] au25 p1_ad[35] au26 p1_ad[36] aw30 p1_ad[37] aw25 p1_ad[38] au23 p1_ad[39] av28 p1_ad[40] au24 p1_ad[41] av22 p1_ad[42] ap23 p1_ad[43] ar23 p1_ad[44] at23 p1_ad[45] aw24 p1_ad[46] au21 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 4 of 30) signal name ball p1_ad[47] au22 p1_ad[48] ap22 p1_ad[49] at22 p1_ad[50] aw23 p1_ad[51] av20 p1_ad[52] ap21 p1_ad[53] ar21 p1_ad[54] at21 p1_ad[55] aw22 p1_ad[56] au20 p1_ad[57] ap20 p1_ad[58] at20 p1_ad[59] aw21 p1_ad[60] av18 p1_ad[61] ar19 p1_ad[62] at19 p1_ad[63] au17 p1_cbe#[0] au14 p1_cbe#[1] av7 p1_cbe#[2] aw13 p1_cbe#[3] aw11 p1_cbe#[4] au19 p1_cbe#[5] ap19 p1_cbe#[6] aw19 p1_cbe#[7] at18 p1_clk_in ar7 p1_clk_out ap8 p1_devsel# ar9 p1_enum# ap16 p1_es au27 p1_frame# ar11 p1_gnt#[1] at6 p1_gnt#[2] av16 p1_gnt#[3] au18 p1_gnt#[4] ar17 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 5 of 30) signal name ball p1_gnt#[5] au15 p1_gnt#[6] at25 p1_gnt#[7] at24 p1_healthy# au6 p1_hs_64en# at27 p1_idsel au4 p1_inta# aw4 p1_intb# aw5 p1_intc# au7 p1_intd# av4 p1_irdy# at9 p1_led# at26 p1_m66en av12 p1_par at11 p1_par64 ap18 p1_pcixcap[0] av26 p1_pcixcap[1] aw27 p1_perr# aw10 p1_pll_avcc ap9 p1_pll_avss ap7 p1_pme# aw9 p1_req#[1] aw3 p1_req#[2] at16 p1_req#[3] aw18 p1_req#[4] ap17 p1_req#[5] at17 p1_req#[6] av24 p1_req#[7] ap24 p1_req64# aw20 p1_rst# at5 p1_rstdir ar13 p1_serr# av8 p1_stop# ap11 p1_trdy# ap10 p2_ack64# ab1 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 6 of 30) signal name ball
intel? gw80314 i/o companion chip package information 56 datasheet p2_ad[0] ae3 p2_ad[1] ae2 p2_ad[2] ae6 p2_ad[3] ac4 p2_ad[4] ad4 p2_ad[5] ad1 p2_ad[6] ad3 p2_ad[7] ad6 p2_ad[8] ac5 p2_ad[9] ab4 p2_ad[10] ac1 p2_ad[11] ac6 p2_ad[12] ab2 p2_ad[13] ab3 p2_ad[14] ab6 p2_ad[15] y5 p2_ad[16] aa1 p2_ad[17] aa2 p2_ad[18] w4 p2_ad[19] y3 p2_ad[20] w3 p2_ad[21] u1 p2_ad[22] w1 p2_ad[23] v5 p2_ad[24] t4 p2_ad[25] v3 p2_ad[26] r1 p2_ad[27] t2 p2_ad[28] t3 p2_ad[29] v4 p2_ad[30] r4 p2_ad[31] p1 p2_ad[32] ap4 p2_ad[33] ap5 p2_ad[34] ap1 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 7 of 30) signal name ball p2_ad[35] an3 p2_ad[36] ap6 p2_ad[37] an1 p2_ad[38] ap3 p2_ad[39] am5 p2_ad[40] am4 p2_ad[41] an2 p2_ad[42] an6 p2_ad[43] al4 p2_ad[44] al3 p2_ad[45] am1 p2_ad[46] al1 p2_ad[47] am3 p2_ad[48] am6 p2_ad[49] ak5 p2_ad[50] ak1 p2_ad[51] al2 p2_ad[52] al6 p2_ad[53] aj4 p2_ad[54] ak4 p2_ad[55] aj1 p2_ad[56] aj3 p2_ad[57] ak6 p2_ad[58] ah5 p2_ad[59] ah1 p2_ad[60] aj2 p2_ad[61] ag4 p2_ad[62] ah4 p2_ad[63] ah3 p2_cbe#[0] ac3 p2_cbe#[1] v2 p2_cbe#[2] y1 p2_cbe#[3] v1 p2_cbe#[4] ag1 p2_cbe#[5] aj6 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 8 of 30) signal name ball p2_cbe#[6] ae1 p2_cbe#[7] ad5 p2_clk_in t5 p2_clk_out u6 p2_devsel# w6 p2_enum# af6 p2_es au1 p2_frame# y4 p2_gnt#[1] m1 p2_gnt#[2] af3 p2_gnt#[3] ag3 p2_gnt#[4] af5 p2_gnt#[5] ag2 p2_gnt#[6] ar1 p2_gnt#[7] ar4 p2_healthy# r2 p2_hs_64en# at1 p2_idsel r3 p2_inta# p3 p2_intb# n1 p2_intc# u3 p2_intd# l1 p2_irdy# u4 p2_led# an4 p2_m66en ad2 p2_par aa4 p2_par64 ah6 p2_pcixcap[0] at3 p2_pcixcap[1] at2 p2_perr# aa3 p2_pll_avcc v6 p2_pll_avss t6 p2_pme# t1 p2_req#[1] m2 p2_req#[2] ag6 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 9 of 30) signal name ball
intel? gw80314 i/o companion chip package information datasheet 57 p2_req#[3] ae4 p2_req#[4] af1 p2_req#[5] af4 p2_req#[6] ar3 p2_req#[7] ar2 p2_req64# ak3 p2_rst# p2 p2_rstdir aa5 p2_serr# w2 p2_stop# aa6 p2_trdy# y6 pbi_ad[0] k36 pbi_ad[1] p35 pbi_ad[2] l34 pbi_ad[3] m35 pbi_ad[4] d33 pbi_ad[5] h37 pbi_ad[6] n34 pbi_ad[7] p34 pbi_ad[8] j37 pbi_ad[9] h35 pbi_ad[10] h36 pbi_ad[11] h39 pbi_ad[12] h38 pbi_ad[13] g39 pbi_ad[14] g36 pbi_ad[15] f36 pbi_ad[16] g38 pbi_ad[17] f39 pbi_ad[18] e37 pbi_ad[19] d39 pbi_ad[20] e38 pbi_ad[21] e34 pbi_ad[22] e36 pbi_ad[23] d37 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 10 of 30) signal name ball pbi_ad[24] c39 pbi_ad[25] d38 pbi_ad[26] e33 pbi_ad[27] c36 pbi_ad[28] d35 pbi_ad[29] b36 pbi_ad[30] f32 pbi_ad[31] c35 pbi_cs#[0] f35 pbi_cs#[1] f37 pbi_cs#[2] g35 pbi_cs#[3] d34 pbi_le g32 pbi_oe# j36 pbi_rdy# k35 pbi_rw f38 pwrup_p1_arb ap26 pwrup_p1_byp av32 pwrup_p1_prim ar25 pwrup_p1_swrst ar26 pwrup_p2_arb aw34 pwrup_p2_byp au36 pwrup_p2_prim au29 pwrup_p2_swrst aw26 pwrup_pbi_bswp aw29 pwrup_trans ap27 pwrup_xs_swrst aw28 ref125m k4 sd_a[0] a20 sd_a[1] a22 sd_a[2] a25 sd_a[3] b26 sd_a[4] a26 sd_a[5] a27 sd_a[6] b27 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 11 of 30) signal name ball sd_a[7] b29 sd_a[8] a28 sd_a[9] a29 sd_a[10] b20 sd_a[11] b30 sd_a[12] a30 sd_a[13] b32 sd_ba[0] a17 sd_ba[1] a19 sd_cas# a13 sd_ckfbi a34 sd_ckfbo b35 sd_clk#[0] b21 sd_clk#[1] b23 sd_clk#[2] b24 sd_clk#[3] b18 sd_clk[0] a21 sd_clk[1] a23 sd_clk[2] a24 sd_clk[3] a18 sd_clken b9 sd_cs#[0] a14 sd_cs#[1] b14 sd_cs#[2] a15 sd_cs#[3] b15 sd_cs#[4] a35 sd_cs#[5] b33 sd_cs#[6] a37 sd_cs#[7] a36 sd_dq[0] d31 sd_dq[1] a31 sd_dq[2] c29 sd_dq[3] e28 sd_dq[4] c34 sd_dq[5] e31 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 12 of 30) signal name ball
intel? gw80314 i/o companion chip package information 58 datasheet sd_dq[6] c30 sd_dq[7] e30 sd_dq[8] a33 sd_dq[9] d30 sd_dq[10] d25 sd_dq[11] c24 sd_dq[12] f29 sd_dq[13] d28 sd_dq[14] e26 sd_dq[15] e25 sd_dq[16] e27 sd_dq[17] f26 sd_dq[18] c25 sd_dq[19] e23 sd_dq[20] c28 sd_dq[21] c27 sd_dq[22] e24 sd_dq[23] f23 sd_dq[24] d24 sd_dq[25] c23 sd_dq[26] c21 sd_dq[27] d19 sd_dq[28] c22 sd_dq[29] d22 sd_dq[30] f19 sd_dq[31] e18 sd_dq[32] c17 sd_dq[33] d16 sd_dq[34] e14 sd_dq[35] c12 sd_dq[36] f17 sd_dq[37] c16 sd_dq[38] c13 sd_dq[39] d13 sd_dq[40] f16 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 13 of 30) signal name ball sd_dq[41] f14 sd_dq[42] f13 sd_dq[43] b12 sd_dq[44] e16 sd_dq[45] e15 sd_dq[46] a12 sd_dq[47] e12 sd_dq[48] c11 sd_dq[49] c10 sd_dq[50] d11 sd_dq[51] d12 sd_dq[52] d8 sd_dq[53] c9 sd_dq[54] d9 sd_dq[55] d10 sd_dq[56] b11 sd_dq[57] a10 sd_dq[58] c8 sd_dq[59] e9 sd_dq[60] a11 sd_dq[61] f12 sd_dq[62] b8 sd_dq[63] a6 sd_dqs[0] e29 sd_dqs[1] f28 sd_dqs[2] c26 sd_dqs[3] f20 sd_dqs[4] c15 sd_dqs[5] e13 sd_dqs[6] a7 sd_dqs[7] a9 sd_dqs[8] c20 sd_dqs[9] c31 sd_dqs[10] d27 sd_dqs[11] f25 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 14 of 30) signal name ball sd_dqs[12] d21 sd_dqs[13] d15 sd_dqs[14] c14 sd_dqs[15] c7 sd_dqs[16] e10 sd_dqs[17] e19 sd_ecc[0] f22 sd_ecc[1] e20 sd_ecc[2] c19 sd_ecc[3] c18 sd_ecc[4] e22 sd_ecc[5] e21 sd_ecc[6] d18 sd_ecc[7] e17 sd_i2c_clk c32 sd_i2c_sda a32 sd_pll_avcc g30 sd_pll_avss d32 sd_pwrdelay c33 sd_ras# b17 sd_vref a8 sd_we# a16 sf_clk aw31 sf_rst# ap25 sram_sku aw33 tck at29 tdi au30 tdo ap28 tms at28 trst# ar27 u0_cts# ar36 u0_dcd# am34 u0_dsr# an36 u0_dtr# am35 u0_ri# at38 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 15 of 30) signal name ball
intel? gw80314 i/o companion chip package information datasheet 59 u0_rts# ar37 u0_rx ap35 u0_tx ar35 u1_cts# ap37 u1_dcd# au39 u1_dsr# an34 u1_dtr# al34 u1_ri# aw37 u1_rts# at37 u1_rx ap36 u1_tx av36 vcc_core f7 vcc_core g7 vcc_core g8 vcc_core h8 vcc_core h9 vcc_core h10 vcc_core h30 vcc_core h31 vcc_core h32 vcc_core j7 vcc_core j8 vcc_core j32 vcc_core k7 vcc_core k8 vcc_core k32 vcc_core l7 vcc_core r16 vcc_core r18 vcc_core r20 vcc_core r22 vcc_core r24 vcc_core t15 vcc_core t17 vcc_core t19 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 16 of 30) signal name ball vcc_core t21 vcc_core t23 vcc_core t25 vcc_core u16 vcc_core u18 vcc_core u20 vcc_core u22 vcc_core u24 vcc_core v15 vcc_core v17 vcc_core v23 vcc_core v25 vcc_core w16 vcc_core w24 vcc_core y15 vcc_core y17 vcc_core y23 vcc_core y25 vcc_core aa16 vcc_core aa24 vcc_core ab15 vcc_core ab17 vcc_core ab23 vcc_core ab25 vcc_core ac16 vcc_core ac18 vcc_core ac20 vcc_core ac22 vcc_core ac24 vcc_core ad15 vcc_core ad17 vcc_core ad19 vcc_core ad21 vcc_core ad23 vcc_core ad25 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 17 of 30) signal name ball vcc_core ae16 vcc_core ae18 vcc_core ae20 vcc_core ae22 vcc_core ae24 vcc_core ak8 vcc_core ak32 vcc_core al8 vcc_core al32 vcc_core am8 vcc_core am9 vcc_core am10 vcc_core am30 vcc_core am31 vcc_core am32 vcc_core an29 vcc_pc f6 vcc_pc g6 vcc_pc h6 vcc_pc h7 vcc_pc j6 vcc_pc k6 vcc_pc m7 vcc_pc n7 vcc_pc p7 vcc_pc r7 vcc_pc t7 vcc_pc u7 vcc_pc v7 vcc_pc w7 vcc_pc y7 vcc_pc aa7 vcc_pc ab7 vcc_pc ac7 vcc_pc ad7 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 18 of 30) signal name ball
intel? gw80314 i/o companion chip package information 60 datasheet vcc_pc ae7 vcc_pc af7 vcc_pc ag7 vcc_pc ah7 vcc_pc aj7 vcc_pc ak7 vcc_pc al7 vcc_pc am7 vcc_pc am33 vcc_pc an8 vcc_pc an9 vcc_pc an10 vcc_pc an11 vcc_pc an12 vcc_pc an13 vcc_pc an14 vcc_pc an15 vcc_pc an16 vcc_pc an17 vcc_pc an18 vcc_pc an19 vcc_pc an20 vcc_pc an21 vcc_pc an22 vcc_pc an23 vcc_pc an24 vcc_pc an25 vcc_pc an26 vcc_pc an27 vcc_pc an28 vcc_pc an30 vcc_pc an31 vcc_pc an32 vcc_pc an33 vcc_pc ap29 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 19 of 30) signal name ball vcc_pc ap30 vcc_pc ap31 vcc_sd f9 vcc_sd f10 vcc_sd f11 vcc_sd f31 vcc_sd g9 vcc_sd g10 vcc_sd g11 vcc_sd g12 vcc_sd g13 vcc_sd g14 vcc_sd g15 vcc_sd g16 vcc_sd g17 vcc_sd g18 vcc_sd g19 vcc_sd g20 vcc_sd g21 vcc_sd g22 vcc_sd g23 vcc_sd g24 vcc_sd g25 vcc_sd g26 vcc_sd g27 vcc_sd g28 vcc_sd g29 vcc_sd g31 vcc_xs f33 vcc_xs f34 vcc_xs g33 vcc_xs g34 vcc_xs h33 vcc_xs h34 vcc_xs j33 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 20 of 30) signal name ball vcc_xs j34 vcc_xs k33 vcc_xs n33 vcc_xs p33 vcc_xs r33 vcc_xs t33 vcc_xs u33 vcc_xs v33 vcc_xs w33 vcc_xs y33 vcc_xs aa33 vcc_xs ab33 vcc_xs ac33 vcc_xs ad33 vcc_xs ae33 vcc_xs af33 vcc_xs ag33 vcc_xs ah33 vcc_xs aj33 vcc_xs ak33 vcc_xs al33 vss_core r15 vss_core r17 vss_core r19 vss_core r21 vss_core r23 vss_core r25 vss_core t16 vss_core t18 vss_core t20 vss_core t22 vss_core t24 vss_core u15 vss_core u17 vss_core u19 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 21 of 30) signal name ball
intel? gw80314 i/o companion chip package information datasheet 61 vss_core u21 vss_core u23 vss_core u25 vss_core v16 vss_core v18 vss_core v19 vss_core v20 vss_core v21 vss_core v22 vss_core v24 vss_core w15 vss_core w17 vss_core w18 vss_core w19 vss_core w20 vss_core w21 vss_core w22 vss_core w23 vss_core w25 vss_core y16 vss_core y18 vss_core y19 vss_core y20 vss_core y21 vss_core y22 vss_core y24 vss_core aa15 vss_core aa17 vss_core aa18 vss_core aa19 vss_core aa20 vss_core aa21 vss_core aa22 vss_core aa23 vss_core aa25 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 22 of 30) signal name ball vss_core ab16 vss_core ab18 vss_core ab19 vss_core ab20 vss_core ab21 vss_core ab22 vss_core ab24 vss_core ac15 vss_core ac17 vss_core ac19 vss_core ac21 vss_core ac23 vss_core ac25 vss_core ad16 vss_core ad18 vss_core ad20 vss_core ad22 vss_core ad24 vss_core ae15 vss_core ae17 vss_core ae19 vss_core ae21 vss_core ae23 vss_core ae25 vss_io b2 vss_io b3 vss_io b7 vss_io b10 vss_io b13 vss_io b16 vss_io b19 vss_io b22 vss_io b25 vss_io b28 vss_io b31 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 23 of 30) signal name ball vss_io b34 vss_io b37 vss_io b38 vss_io c2 vss_io c3 vss_io c37 vss_io c38 vss_io d4 vss_io d14 vss_io d17 vss_io d20 vss_io d23 vss_io d26 vss_io d29 vss_io d36 vss_io e6 vss_io e8 vss_io e11 vss_io e32 vss_io e35 vss_io e39 vss_io f15 vss_io f18 vss_io f21 vss_io f24 vss_io f27 vss_io f30 vss_io g3 vss_io g37 vss_io j39 vss_io k3 vss_io l35 vss_io m6 vss_io m38 vss_io n2 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 24 of 30) signal name ball
intel? gw80314 i/o companion chip package information 62 datasheet vss_io n35 vss_io p38 vss_io r5 vss_io r35 vss_io t38 vss_io u2 vss_io u5 vss_io u35 vss_io v38 vss_io w5 vss_io w35 vss_io y2 vss_io y38 vss_io aa35 vss_io ab5 vss_io ab38 vss_io ac2 vss_io ac35 vss_io ad38 vss_io ae5 vss_io ae35 vss_io af2 vss_io af38 vss_io ag5 vss_io ag35 vss_io ah2 vss_io ah38 vss_io aj5 vss_io aj35 vss_io ak2 vss_io ak38 vss_io al5 vss_io al35 vss_io am2 vss_io am38 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 25 of 30) signal name ball vss_io an5 vss_io an7 vss_io an35 vss_io ap2 vss_io ap33 vss_io ap34 vss_io ar5 vss_io ar10 vss_io ar12 vss_io ar14 vss_io ar16 vss_io ar18 vss_io ar20 vss_io ar22 vss_io ar24 vss_io ar28 vss_io at4 vss_io at36 vss_io au2 vss_io au3 vss_io au32 vss_io au37 vss_io au38 vss_io av2 vss_io av3 vss_io av6 vss_io av9 vss_io av11 vss_io av13 vss_io av15 vss_io av17 vss_io av19 vss_io av21 vss_io av23 vss_io av25 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 26 of 30) signal name ball vss_io av29 vss_io av37 vss_io av38 xs_a[0] ah34 xs_a[1] ag38 xs_a[2] ag39 xs_a[3] ag37 xs_a[4] af36 xs_a[5] aj34 xs_a[6] ah37 xs_a[7] ah39 xs_a[8] af37 xs_a[9] ak34 xs_a[10] aj36 xs_a[11] ah35 xs_a[12] ag36 xs_a[13] af35 xs_a[14] ah36 xs_a[15] aj39 xs_abort af34 xs_be[0] ac36 xs_be[1] ad34 xs_be[2] ac37 xs_be[3] ac39 xs_be[4] ad39 xs_be[5] ac38 xs_be[6] ae34 xs_be[7] ae36 xs_clk k38 xs_cwf ae37 xs_dq[0] y35 xs_dq[1] y37 xs_dq[2] y36 xs_dq[3] w38 xs_dq[4] y39 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 27 of 30) signal name ball
intel? gw80314 i/o companion chip package information datasheet 63 xs_dq[5] aa34 xs_dq[6] y34 xs_dq[7] w37 xs_dq[8] v34 xs_dq[9] u37 xs_dq[10] t35 xs_dq[11] u36 xs_dq[12] u39 xs_dq[13] u34 xs_dq[14] t37 xs_dq[15] t39 xs_dq[16] n38 xs_dq[17] p36 xs_dq[18] n37 xs_dq[19] n36 xs_dq[20] l38 xs_dq[21] p37 xs_dq[22] n39 xs_dq[23] m39 xs_dq[24] an38 xs_dq[25] an37 xs_dq[26] an39 xs_dq[27] al38 xs_dq[28] am39 xs_dq[29] al39 xs_dq[30] al37 xs_dq[31] am37 xs_dq[32] w39 xs_dq[33] v37 xs_dq[34] v36 xs_dq[35] w36 xs_dq[36] v39 xs_dq[37] w34 xs_dq[38] v35 xs_dq[39] u38 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 28 of 30) signal name ball xs_dq[40] r38 xs_dq[41] t34 xs_dq[42] t36 xs_dq[43] r36 xs_dq[44] r39 xs_dq[45] r34 xs_dq[46] r37 xs_dq[47] p39 xs_dq[48] j38 xs_dq[49] k37 xs_dq[50] l36 xs_dq[51] k39 xs_dq[52] l37 xs_dq[53] l39 xs_dq[54] m37 xs_dq[55] m36 xs_dq[56] aj37 xs_dq[57] ak36 xs_dq[58] al36 xs_dq[59] aj38 xs_dq[60] ak35 xs_dq[61] ak37 xs_dq[62] ak39 xs_dq[63] am36 xs_dvalid[0] aa36 xs_dvalid[1] ab34 xs_ecc[0] aa38 xs_ecc[1] aa39 xs_ecc[2] aa37 xs_ecc[3] ab35 xs_ecc[4] ac34 xs_ecc[5] ab36 xs_ecc[6] ab39 xs_ecc[7] ab37 xs_fiq[0] ar39 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 29 of 30) signal name ball xs_fiq[1] ar38 xs_hlda[0] ag34 xs_hlda[1] ae38 xs_hold[0] ae39 xs_hold[1] af39 xs_irq[0] ap39 xs_irq[1] ap38 xs_len[0] ad36 xs_len[1] ad37 xs_len[2] ad35 xs_pll_avcc l33 xs_pll_avss m34 xs_reset# at39 table 21 1025-lead hsbga package ? alphabetical signal listing (sheet 30 of 30) signal name ball
intel? gw80314 i/o companion chip package information 64 datasheet 3.2 package thermal specifications the device is specified for operation when t c (case temperature) is within the range of 0 c to 85 c, depending on operating conditions. case temperature may be measured in any environment to determine whether the processor is within specified operating range. case temperature is best measured at the center of the top surface, opposite the ball pad. 3.2.1 thermal characteristics table 22 summarizes the thermal simulation data for the gw80314. the thermal performance of the gw80314 package is represented by the following parameters: 1. jt , thermal characterization parameter from junction-to-top center jt = (t j - t t ) / p where t t is the temperature of the top-center of the package jt is used to estimate junction temperature by measuring t t in an actual environment jt simulations are carried out to show the thermal performance of the gw80314.
intel? gw80314 i/o companion chip package information datasheet 65 table 22. thermal simulation data for the intel ? gw80314 i/o processor package conditions package type hsbga ball count 1025 package size (mm) 40x40 mold thickness (mm) 1.17 pitch (mm) 1 ball matrix (mm) 39x39 ball row depth 7x7 thermal ball matrix 11x11 vias 144 pad size (mm) 12.5x12.5 die size (mm) 11.62x11.62 substrate layer 4 substrate thickness (mm) 0.56 pcb conditions (jedec jesd51-9) pcb layer 4 pcb dimensions (mm) 127.0x139.5 pcb thickness (mm) 1.6 environment conditions maximum junction temperature (c) 125 power dissipation (w) 2.456 typical 4.226 max thermal data property v air (m/s) psi jt (c/w) 0.00 1.8 1.00 1.8 2.00 1.8 heat flow path heat dissipated from pcb (%) 66.1 (%) 15.9 heat dissipated from others (%) 18.0
intel? gw80314 i/o companion chip package information 66 datasheet 3.2.2 case temperature when measuring case temperature, t c , attention to detail is requir ed to ensure accuracy. when a thermocouple is used, calibrate is before taking measurements. errors may result when the measured surface temperature is affected by the su rrounding ambient air temperature. such errors may be due to a poor thermal contact between ther mocouple junction and the surface, heat loss by radiation, or conduction through thermocouple leads. to minimize measurement errors: ? use a 35 gauge k-type thermocouple or equivalent. ? attach the thermocouple bead or junction to the package top surface at a location corresponding to the center of the die. th e center of the die gives a more accurate measurement and less variation as the boundary condition changes. ? attach the thermocouple bead at a 0 o angle with respect to the p ackage when no heat sink is attached. 3.3 socket information table 23 and table 24 provide vendor details for socket-headers and burn-in sockets for the gw80314. this is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. 3.3.1 socket-header vendor table 23. socket-header vendor company factory representative phone/fax # bga 544-pin socket carrier advanced interconnections tbd tbd socket: fhsb1025-716gg carrier: fhax1025-715g ironwood tbd tbd sg-bga-6035
intel? gw80314 i/o companion chip package information datasheet 67 3.3.2 burn-in socket vendor 3.3.3 shipping tray vendor table 24. burn-in socket vendor company factory representative phone # burn-in socket part # tbd tbd tbd tbd table 25. shipping tray vendor company factory representative phone # shipping tray part # peak 2136a rutland drive austin, texas 78758 tbd 512-339-4684 nxbg40402.503076rev.e
intel? gw80314 i/o companion chip electrical specifications 68 datasheet 4.0 electrical specifications 4.1 absolute maximum ratings table 26. maximum temperature and voltage ratings parameter maximum rating storage temperature t stg ?40 c to +125 c case temperature under bias t c 0 c to + 85 c supply voltage v cc33 with regard to v ss ?0.5 v to +4.1 v (3.3 vdc) supply voltage v cc25 with regard to v ss ?0.5 v to +3.6 v (2.5 vdc) supply voltage v cc12 with regard to v ss ?0.5 v to +2.0 v (1.2 vdc) warning: stressing the device beyond the ?absolute ma ximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operatin g conditions? may affect device reli ability. table 27. operating conditions symbol parameter min. max. units notes pvcc33 3.3 v supply power 756 1710 mw pvcc25 2.5 v supply power 270 609 mw pvcc12 1.2 v supply power 1430 1907 mw v cc33 3.3 v supply power 3.0 3.6 v v cc25 2.5 v supply power 2.3 2.7 v v cc12 1.2 v supply power 1.08 1.32 v v pll pll analog supply voltage 3.0 3.6 v i pll pll analog supply current ? 10 ma warning: stressing the device beyond the ?absolute maxi mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reli ability.
intel? gw80314 i/o companion chip electrical specifications datasheet 69 4.2 pll supply pin requirements package balls of the supply pins for the four phase lock loops (plls) used on the gw80314 should be isolated and decoupled externally in order to provide the cleanest possible supply environment. the following pins are used as pll supplies in the gw80314: xs_pll_avcc, sd_pll_avcc, p1_pll_avcc, and p2_pll_avcc. the recommended decoupling network for these pins is shown in figure 5 . in order to minimize the transient ir drops across the leads from the isolation network and the pll supply device pins, the trace routes must be kept short. it is preferred that the cripple capacitor used in figure 5 be placed as close to the device pins as possible, on the backside of the board underneath the device, when possible. figure 5. intel ? gw80314 i/o processor pll supply decoupling network b1331-01 device note: lfilter must be a high srf smt wire wound rf indicator avcc pll_avcc pll_avss lfilter ofilter 4.7f (min) 3.3f (max) cripple 0.1f 0.5 ? (min) 4 ? (max) 470h (min) 4.7h (max) (rf smt) note: ofilter must be a low esr tantalum smt capacitor note: the trace routing resistance must be less than 0.1 ? to cripple note: the trace routing and the rdc of the inductor accounts for this resistance, and should be in the range shown note: the vcc to vss 0.1 f decoupling cap needs to be as close to the device pins as possible. capacitors should be low esr (high frequency) ceramic chip capacitors
intel? gw80314 i/o companion chip electrical specifications 70 datasheet 4.3 targeted dc specifications table 28. dc characteristics symbol parameter minimum maximum units notes v il1 sdram input low voltage -0.3 v ref - 0.12 v - v ih1 sdram input high voltage v ref + 0.12 v cc25 + 0.3 v - v il2 misc. input low voltage -0.3 0.8 v 1 v ih2 misc. input high voltage 2.0 v cc33 + 0.5 v 1 v il3 gige input low voltage -0.3 0.8 v v ih3 gige input high voltage 2.0 v cc33 + 0.5 v 4 v il4 pci-x input low voltage -0.5 0.35*v cc33 v2 v ih4 pci-x/pci input high voltage 0.5*v cc33 v cc33 + 0.5 v 2 v il5 pci input low voltage -0.5 0.3*v cc33 v2 v ol1 misc. output low voltage - 0.4 v i ol = 6ma, 1, 5 v oh1 misc. output high voltage v cc33min - 0.5 - v i ol = -6ma, 1, 5 v ol2 sdram output low voltage - 0.54 v i ol = 7.6ma v oh2 sdram output high voltage v cc25 - 0.54 - v i ol = -7.6ma v ol3 intel xscale ? output low voltage - 0.4 v i ol = 8ma, 5 v oh3 intel xscale ? output high voltage v cc33min - 0.5 - i ol = -8ma, 4, 5 v ol4 pci-x output low voltage - 0.1*v cc33 vi ol = 1500 a, 2 v oh4 pci-x output high voltage 0.9*v cc33 -vi ol = -500 a, 2 v ol5 gige output low voltage - 0.4 v i ol = 12ma, 5 v oh5 gige output high voltage v cc33min - 0.5 - v i ol = -12ma,4, 5 c in input pin capacitance - 8 pf 2, 3 c clk clock pin capacitance 5 8 pf 2, 3 l pin ball inductance - 22 nh 2, 3 notes: 1. miscellaneous signals include all signals that are not pci, gige, intel xscale ? , or sdram signals. 2. as required by the pci-x addendum to the pci local bus specification, revision 1.0a. 3. not tested. 4. i/o power supply 5. v cc12 min. = 1.08 v, v cc33min = 3.0 v.
intel? gw80314 i/o companion chip electrical specifications datasheet 71 4.4 targeted ac specifications the following section details the ac speci fications for gw80314 signal interfaces. 4.4.1 pci/x clock signal timings table 29. pci/x clock timings symbol parameter pci-x pci units notes min. max. min. max. t f1 pci clock frequency 50 133 25 66 mhz 1,2 t c1 pci clock cycle time 7.5 20 15 40 ns 1,3 t ch1 pci clock high time 3 - 6 - ns t cl1 pci clock low time 3 - 6 - ns t sr1 pci clock slew rate 1 6 1 6 v/ns 4 spread spectrum requirements f mod pci clock modulation frequency 30 33 30 33 khz f spread pci clock frequency spread -1 0 -1 0 % notes: 1. the clock frequency may not change bey ond the spread-spectrum limits except while sfn_rst# is asserted. 2. the pci output clock is limited to sfn_clk, sfn_clk/2, sfn_clk/4. 3. the minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 4. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform. table 30. ddr sdram clock timings symbol parameter pc 266 units min. max. t f2 ddr sdram clock frequency 66 100 mhz t c2 ddr sdram clock cycle time 10 - ns t ch2 ddr sdram clock high time 4.5 5.5 ns t cl2 ddr sdram clock low time 4.5 5.5 ns t cs2 ddr sdram clock period stability - +/-90 ps t skew2 ddr sdram clock skew for sd_clk[2:0] and sd_clk#[3:0] - 240 ps
intel? gw80314 i/o companion chip electrical specifications 72 datasheet 4.4.2 dual-gigabit ethernet (gige) interface signal timings table 31. intel xscale ? microprocessor clock timings symbol parameter xs 100 xs 75 units min. max. min. max. t f3 intel xscale ? microprocessor clock frequency - 100 - 75 mhz t c3 intel xscale ? microprocessor clock cycle time 10 - 13 - ns t ch3 intel xscale ? microprocessor clock high time 3 - 5 - ns t cl3 intel xscale ? microprocessor clock low time 3 - 5 - ns t cs3 intel xscale ? microprocessor clock period stability - +/-175 - +/-175 ps table 32. ac specifications for mii management interface symbol parameter condition min. max. units t permdc period of mdc mii management clock output - 60 ns t pwmdc pulse width of mdc output - 16 ns t pdmdio propagation delay of mdio output from rising edge of mdc - 7.5 ns t sumdio input setup time of mdio to rising edge of mdc - 4 ns t hmdio input hold time of mdio after rising edge of mdc - 3 ns note: mdc mii management interface clock period is equal to one of the following: sfn_clk/8, sfn_clk/16, sfn_clk/28, sfn_clk/40, sfn_clk/56.
intel? gw80314 i/o companion chip electrical specifications datasheet 73 table 33 lists the ac specifications for the g/mii interface of the dual gige controller. for propagation delays, the ac loads are assumed to be transmission lines, so numbers quoted in the specifications assume driving a 50 ohm load connected to a voltage source = v ccio /2. table 33. ac specifications for g/mii and tbi interface symbol parameter condition min. max. units t ctxclk period of e[x]_txclk inputs 10mb/s mode 399.98 400.02 ns 100mb/s mode 39.998 40.002 ns t cgtxclk period of gtx_clk input 1000mb/s mode 7.9992 8.0008 ns t pwtxclk pulse width of e[x]_txclk inputs 10mb/s mode 180 220 ns 100mb/s mode 18 22 ns t pwgtxclk pulse width of gtx_clk input 1000mb/s mode 3.2 4.8 ns t crxclk period of e[x]_rxclk inputs 10mb/s mode 399.98 400.02 ns 100mb/s mode 39.998 40.002 ns 1000mb/s mode 7.9992 8.0008 ns t cpmarclk period of pma_clk[x] input 1000mb/s mode 15.9984 16.0016 ns t pwrxclk pulse width of e[x]_rxclk input 10mb/s mode 180 220 ns 100mb/s mode 18 22 ns 1000mb/s mode 3.2 4.8 ns t pwpmarclk pulse width of pma_clk[x] input 1000mb/s mode 6.4 9.6 ns t skpma skew between pma_clk[x] inputs 1000mb/s mode 7.5 8.5 ns t pdtx propagation delay of e[x]_tcg after rising edge of e[x]_txclk 10mb/s or 100mb/s mode -12ns t pdgtx propagation delay of e[x]_txg after rising edge of gtx_clk 1000mb/s mode - 5 ns t surx setup time for e[x]_rcg to rising edge of e[x]_rxclk 10,100,1000mb/s modes 2ns t hrx hold time for e[x]_rcg to rising edge of e[x]_rxclk g/mii modes 0 ns notes: 1. all parameters are valid for both ports of gige interface (i.e., e[x] = e0 or e1).
intel? gw80314 i/o companion chip electrical specifications 74 datasheet 4.4.3 pci/x interface signal timings table 34. ac specifications for pci/x interface symbol parameter pci-x 133 pci-x 66 pci 66 pci 33 units notes min. max. min. max. min. max. min. max. t ov1 clock to output valid delay for bused signals 0.7 3.8 0.7 3.8 1 6 2 11 ns 1,2,3 t ov2 clock to output valid delay for point to point signals 0.7 3.8 0.7 3.8 2 6 2 12 ns 1,2,3 t of clock to output float delay - 7 - 7 - 14 - 28 ns 1,7 t is1 input setup to clock for bused signals 1.2 - 1.7 - 3 - 7 - ns 3,4,8 t is2 input setup to clock for point to point signals 1.2 - 1.7 - 5 - 10,12 - ns 3,4 t ih1 input hold time from clock 0.5 - 0.5 - 0 - 0 - ns 4 t rst reset active time 1-1-1-1-ms t rf reset active to output float delay - 40 - 40 - 40 - 40 ns 5,6 t is3 p[x]_req64# to reset setup time 10 - 10 - 10 - 10 - clocks t ih2 reset to p[x]_req64# hold time -0.6 50 -0.6 50 -0.6 50 -0.6 50 ns t is4 pci-x initialization pattern to reset setup time 10-10-----clocks t ih3 reset to pci-x initialization pattern hold time -0.650-0.650----ns t srst assertion of reset slew rate for battery backup entry 20 20 20 20 ns/v 9 notes: 1. see the timing measurement conditions in figure 10 . 2. see figure 15 , figure 16 and figure 17 . 3. setup time for point-to-point signals applies to p[x]_req# and p[x]_gnt# only. all other signals are bused. 4. see the timing measurement conditions in figure 9 . 5. sfn_rst# is asserted and deasserted asynchronously with respect to sfn_clk. 6. all output drivers must be floated when sfn_rst# is active. 7. for purposes of active/float timing measurements, the hi-z or ?off? state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. setup time applies only when the device is not driving the pi n. devices cannot drive and receive signals at the same time. 9. relevant reset input pin depends on power-on configur ation and may be p1_rst#, p2_rst#, or sfn_rst#. this specification does not apply to systems that do not implement batte ry backup. per pci/x specifications reset slew rate is only specified for the de-assertion edge at 20ns/v.
intel? gw80314 i/o companion chip electrical specifications datasheet 75 4.4.4 ddr sdram interface signal timings 4.4.5 intel xscale ? microprocessor interface signal timings table 35. ac specifications for ddr sdram interface symbol parameter min. max. units notes t vb1 sd_dqs output valid time before sd_clk - 0.9 ns 1 t va1 sd_dqs output valid time after sd_clk - 0.9 ns 1 t vb2 address and control write output valid before sd_clk 3.9 - ns 1 t va2 address and control write output valid after sd_clk 4.3 - ns 1 t vb3 sd_dqs read input valid time before sd_ dq - 0.9 ns 2 t va3 sd_dqs read input valid time after sd_dq - 0.9 ns 2 t vb4 sd_dqs write input valid time before sd_ dq 1.7 - ns 1 t va4 sd_dqs write input valid time after sd_dq 1.7 - ns 1 notes: 1. see figure 12 . 2. see figure 13 . table 36. ac specifications for intel xscale ? microprocessor interface symbol parameter min. max. units notes t ov1 output valid delay from xs_clk - xs_dq[63:0] and xs_be[7:0] 3.2 8.5 ns 1,3 t ov2 output valid delay from xs_clk - xs_dvalid and xs_abort 3.2 8.5 ns 1,3 t is1 input setup to xs_clk - xs_dq[63:0] and xs_be[7:0] 0.5 - ns 2 t ih1 input hold from xs_clk - xs_dq[63:0],xs_be[7:0] 2.2 - ns 2 t is2 input setup to xs_clk - xs_a[15:0], xs_len[2:0] 0.5 - ns 2 t ih2 input hold from xs_clk - xs_a[15:0],xs_len[2:0] 2.2 - ns 2 notes: 1. see figure 10 . 2. see figure 9 . 3. these output valid times are specified with 30 pf loading.
intel? gw80314 i/o companion chip electrical specifications 76 datasheet 4.4.6 uart interface signal timings table 37. ac specifications for uart interface symbol parameter minimum max. units notes t hdsr u[x]_dsr# hold time 0 - ns t sdsr u[x]_dsr# setup time 60 - ns t drdsr u[x]_rts# - u[x]_dsr# delay time 30 - ns t dwdsr u[x]_cts# - u[x]_dsr# delay time 30 - ns t hrx u[x]_rx hold time 30 - ns t srx u[x]_rx setup time 30 - ns t dtx u[x]_tx transmit cycle delay time 125 - ns t hrts u[x]_dsr# - u[x]_rts# hold time 20 - ns t drts u[x]_rts# - u[x]_tx data delay time - 60 ns 1 t dfrts u[x]_rts# - u[x]_tx floating data delay time - 100 ns 1 t drx u[x]_rx receive cycle delay time 150 - ns t hcts u[x]_dsr# - u[x]_cts# hold time 20 - ns notes: 1. output has external load of 100pf. charge and discharge times determined by v ol , v oh , and external load.
intel? gw80314 i/o companion chip electrical specifications datasheet 77 4.4.7 peripheral bus interface (pbi) signal timings table 38. pbi interface timing parameter timing relationship min. max. units notes t sadle setup time from address valid to pbi_le assertion -6.0 + w ns 1 t hadle hold time from pbi_le assertion to address release 7.5 + w 1 , 2 t sadcs setup time from address valid to pbi_cs_b assertion -7.5 + w ns 1 t dacsoe delay time from pbi_cs_b assertion to pbi_oe_b assertion -1.0 + w 2.5 + w ns 1 t dacswe delay time from pbi_cs_b assertion to pbi_rw assertion 0.0 + w 2.0 + w ns 1 t hwdcs hold time from pbi_cs_b deassertion to data release for write data 0.5 ns t ddcswe delay time from pbi_cs_b deassertion to pbi_rw deassertion in handshaking mode -2.0 + w 0.0 + w ns 1 t dhwecs delay time from pbi_rw deassertion to pbi_cs_b deassertion in non-handshaking mode 0.0 + w 2.0 + w ns 1 t ddcsoe delay time from pbi_cs_b deassertion to pbi_oe_b deassertion -1.0 2.5 ns t vadrd delay time from address valid to read data valid in latch mode 2.1 + w ns 1 , 3 t wvrd data valid window 3.7 ns t vadwd write data valid after address is released in latch mode 4.5 ns t vcswd write data valid after pbi_cs_b assertion in non-latch mode 7.5 ns notes: 1. can be programmed to multiple integer sfn clock cycles. as suming programmed to least amount of integer clock cycles. note that ?+w? indicates programmable wait states. 2. calculation includes one sfn clock cycle with a period of 7.5 ns. 3. calculation includes two sfn clock cycles. sfn clock cycle period is 7.5 ns.
intel? gw80314 i/o companion chip electrical specifications 78 datasheet figure 6. address window signal timing diagram note: all timing relationships are independent of each other. t sadle t sadcs t dacsoe t dacswe address valid pbi_le pbi_ad pbi_cs_b pbi_oe_b pbi_rw t hadle write data valid pbi_ad t vcswd t vadwd write data valid
intel? gw80314 i/o companion chip electrical specifications datasheet 79 figure 7. data window signal timing diagram figure 8. address to read data timing diagram t hwdcs t ddcswe t dhwecs write data valid pbi_ad pbi_cs_b pbi_rw t ddcsoe pbi_oe_b address valid pbi_ad address valid data valid t vadrd pbi_ad t wvrd
intel? gw80314 i/o companion chip electrical specifications 80 datasheet 4.4.8 i 2 c interface signal timings table 39 lists the ac specifications for gw80314 i 2 c interfaces. the specifications are valid for both the gpio i 2 c interface and the i 2 c interface contained within the ddr sdram controller. table 39. ac specifications for i 2 c interface symbol parameter std. mode units notes min. max. f scl sd_i2c_clk/i2c_sclk clock frequency 0 100 khz t buf bus free time between stop and start condition 4.7 - s1 t hdsta hold time (repeated) start condition 4 - s1,3 t low sd_i2c_clk/i2c_sclk clock low time 4.7 - s1,2 t high sd_i2c_clk/i2c_sclk clock high time 4 - s1,2 t susta setup time for a repeated start condition 4.7 - s1 t hddat data hold time 0 3.45 s1 t sudat data setup time 250 - ns 1 t sr sd_i2c_clk, sd_i2c_sda, i2c_sclk, and i2c_sda rise time - 1000 ns 1 t sf sd_i2c_clk, sd_i2c_sda, i2c_sclk, and i2c_sda fall time - 300 ns 1 t susto setup time for stop condition 4 - s1 notes: 1. see figure 11 . 2. not tested. 3. after this period, the first clock pulse in generated.
intel? gw80314 i/o companion chip electrical specifications datasheet 81 4.4.9 boundary scan test signal timings table 40. boundary scan test signal timings symbol parameter min. max. units notes t bsf tck frequency 0 10 mhz t bsch tck high time 50 - ns measured at 1.5v, 1 t bscl tck low time 50 - ns measured at 1.5v, 1 t bscr tck rise time - 25 ns 0.8v to 2.0v, 1 t bscf tck fall time - 25 ns 2.0v to 0.8v, 1 t sis1 input setup to tck 10 - ns 4 t bsih1 input hold from tck 10 - ns 4 t bsov1 tdo output valid delay from falling edge of tck. - 15 ns 2, 3 t of1 tdo output float delay from falling edge of tck - 15 ns 2, 5 notes: 1. not tested. 2. outputs precharged to v cc5 . 3. see figure 10 . 4. see figure 9 . 5. a float condition occurs when the output current becomes less than i lo . float delay is not tested. see figure 10 .
intel? gw80314 i/o companion chip electrical specifications 82 datasheet 4.5 ac timing waveforms figure 9. input timing measurement waveforms figure 10. output timing measurement waveforms clk input valid v test v test v test t is t ih v tl v th v th v tl v max v test clk output float vtrise output delay rise output delay fall v tfall t ov t ov t of v tl v th
intel? gw80314 i/o companion chip electrical specifications datasheet 83 figure 11. i 2 c interface signal timings figure 12. ddr sdram write timings sda scl t buf stop start t low t hdsta t high t sr t hddat t sf t sudat t susta repeated t hdsta t sp stop t susto start sd_clk sd_dqs sd_dq t va1 t vb1 t vb4 t va4 t vb2 t va2 addr/ctrl
intel? gw80314 i/o companion chip electrical specifications 84 datasheet figure 13. ddr sdram read timings sd_dqs sd_dq t vb3 t va3 sd_clk
intel? gw80314 i/o companion chip electrical specifications datasheet 85 4.6 ac test conditions table 41 and figure 14 through figure 17 summarize the ac test and measurement conditions to be used for the gw80314. table 41. ac measurement conditions symbol pci-x pci ddr intel xscale ? microprocessor gige units notes v tch 0.6*v cc33 0.6*v cc33 -0.6*v cc33 0.6*v cc33 v v tcl 0.2*v cc33 0.2*v cc33 -0.2*v cc33 0.2*v cc33 v v th 0.6*v cc33 0.6*v cc33 2.0 0.6*v cc33 0.6*v cc33 v v tl 0.25*v cc33 0.2*v cc33 0.5 0.2*v cc33 0.2*v cc33 v v test 0.4*v cc33 0.4*v cc33 1.25 0.4*v cc33 0.4*v cc33 v v trise 0.285*v cc33 0.285*v cc33 1.25 0.285*v cc33 0.285*v cc33 v v fall 0.615*v cc33 0.615*v cc33 1.25 0.615*v cc33 0.615*v cc33 v v max 0.4*v cc33 0.4*v cc33 1.5 0.4*v cc33 0.4*v cc33 v slew rate 1 - 6 1 - 6 1.5 1.5 1.5 v/ns 1 note: input signal slew rate is measured between v il and v ih . figure 14. ac test load for all signals except pci and ddr sdram figure 15. pci/pci-x t ov(max) rising edge ac test load output 50pf te s t point output te s t point 10pf 25 ?
intel? gw80314 i/o companion chip electrical specifications 86 datasheet figure 16. pci/pci-x t ov(max) falling edge ac test load figure 17. pci/pci-x t ov(min) ac test load output 10pf 25 ? v cc33 te st point output te st point 10pf 1k ? 1k ? v cc33
intel? gw80314 i/o companion chip electrical specifications datasheet 87 4.7 power sequencing the power-up and power-down sequences for the 1.2 v/2.5 v/3.3 v supply rails are specified below: ? the 1.2 v rail can be ramped before the 2.5 v and/or 3.3 v rails. ? current transients can occur when the 1.2 v su pply is ramped after the 2.5 v and/or 3.3 v supply rails. ? the transients are acceptable when the 1.2 v lag is less than or equal to 20 ms. ? transient currents of up to 2 a/v dd2.5 and 4 a/v dd3.3 can occur on the supplies until v dd1.2 >= ~0.6 v. ? the 1.2 v supply can power-down before 3.3 v/2.5 v by no more than 20 ms, or any time after. these requirements are illustrated in figure 18 . power-sequencing rules must be applied for both power-up and power-down. while only power-up sequencing is described in the graphs and paragraphs below, power-down sequencing must comply with the same rules. figure 18. correct power sequence for v dd33 , v dd25 , and v dd12 volts 1.2 3.3 2.5 vdd3.3 0.5 vdd2.5 vdd1.2 ? vdd 3.3 and vdd 2.5 can come up in either order relative to each other ? vdd 1.2 can proceed v3.3 and vdd 2.5 or lag up to 20ms max ? if vdd 1.2 lags vdd 3.3 and/or vdd 2.5 transient currents of up to 2a/vdd 2.5 and 4a/vdd 3.3 occur on the supplies until vdd 1.2 >= ~0.6v ? 1.2v can power down before 3.3v/2.5v by no more than 20ms or any time after 3.3v/2.5v. time 10ms max vdd 3.3 and vdd 2.5 in either order volts 1.2 3.3 2.5 vdd3.3 0.5 vdd2.5 vdd1.2 ? vdd 3.3 and vdd 2.5 can come up in either order relative to each other ? vdd 1.2 can proceed v3.3 and vdd 2.5 or lag up to 20ms max ? if vdd 1.2 lags vdd 3.3 and/or vdd 2.5 transient currents of up to 2a/vdd 2.5 and 4a/vdd 3.3 occur on the supplies until vdd 1.2 >= ~0.6v ? 1.2v can power down before 3.3v/2.5v by no more than 20ms or any time after 3.3v/2.5v. time 10ms max vdd 3.3 and vdd 2.5 in either order
intel? gw80314 i/o companion chip electrical specifications 88 datasheet this page intentionally left blank

▲Up To Search▲

Price & Availability of GW80314GSSL7NK

	To Download GW80314GSSL7NK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .